公开(公告)号：US11887660B2

公开(公告)日：2024-01-30

申请号：US17894191

申请日：2022-08-24

Applicant: MEDIATEK INC.

Inventor： Yi-Ping Kuo ,  Yi-Te Chiu

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal.

公开(公告)号：US10541023B2

公开(公告)日：2020-01-21

申请号：US16019464

申请日：2018-06-26

Applicant: MEDIATEK INC.

Inventor： Chia-Wei Wang ,  Yi-Te Chiu ,  Wen-Pin Hsieh

IPC: G11C11/41 ,  G11C11/419 ,  G11C5/00

Abstract: A data line control circuit has a data line driving circuit and a write-assist data line driving circuit. The data line driving circuit is used to drive differential data lines during a write operation of at least one memory cell. The write-assist data line driving circuit is used to drive at least one write-assist data line during the write operation of the at least one memory cell, wherein the at least one write-assist data line is isolated from the differential data lines, and is driven to have a first voltage transition from a first voltage level to a second voltage level, such that one of the differential data lines has a second voltage transition from a third voltage level to a fourth voltage level that is induced by the first voltage transition via capacitive coupling.

公开(公告)号：US20190108890A1

公开(公告)日：2019-04-11

申请号：US16211524

申请日：2018-12-06

Applicant: MEDIATEK Inc.

Inventor： Chia-Wei Wang ,  Shu-Lin Lai ,  Yi-Te Chiu

IPC: G11C17/18 ,  G11C7/06

CPC classification number: G11C17/18 ,  G11C7/06 ,  G11C7/067

Abstract: A sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, an adaptive keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The adaptive keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened.

公开(公告)号：US20190074054A1

公开(公告)日：2019-03-07

申请号：US16019464

申请日：2018-06-26

Applicant: MEDIATEK INC.

Inventor： Chia-Wei Wang ,  Yi-Te Chiu ,  Wen-Pin Hsieh

IPC: G11C11/419

Abstract: A data line control circuit has a data line driving circuit and a write-assist data line driving circuit. The data line driving circuit is used to drive differential data lines during a write operation of at least one memory cell. The write-assist data line driving circuit is used to drive at least one write-assist data line during the write operation of the at least one memory cell, wherein the at least one write-assist data line is isolated from the differential data lines, and is driven to have a first voltage transition from a first voltage level to a second voltage level, such that one of the differential data lines has a second voltage transition from a third voltage level to a fourth voltage level that is induced by the first voltage transition via capacitive coupling.

公开(公告)号：US20180114583A1

公开(公告)日：2018-04-26

申请号：US15492014

申请日：2017-04-20

Applicant: MEDIATEK Inc.

Inventor： Chia-Wei Wang ,  Shu-Lin Lai ,  Yi-Te Chiu

IPC: G11C17/18

CPC classification number: G11C17/18 ,  G11C7/06 ,  G11C7/067

Abstract: A sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, an adaptive keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The adaptive keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened.