公开(公告)号：US20170091101A1

公开(公告)日：2017-03-30

申请号：US15373038

申请日：2016-12-08

Applicant: MediaTek Inc.

Inventor： Chien-Hung Lin ,  Tung-Yao Lee

IPC: G06F12/0831

CPC classification number: G06F12/0831 ,  G06F2212/1016 ,  G06F2212/621 ,  Y02D10/13

Abstract: Techniques and examples pertaining to memory coherence management with a snoop mechanism and snoop filter structure for multi-port processors are described. A method may involve receiving a request from a first processor having a first plurality of local memories and more than one snoop ports. Responsive to the request, the method may involve snooping one or more snoop ports of a second processor having a second plurality of local memories without snooping any of the more than one snoop ports of the first processor.

公开(公告)号：US09575893B2

公开(公告)日：2017-02-21

申请号：US14820571

申请日：2015-08-07

Applicant: MEDIATEK INC.

Inventor： Chien-Hung Lin ,  Wei-Hao Chiao

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F12/0824 ,  G06F12/0833 ,  G06F12/0842 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/283 ,  G06F2212/608

Abstract: A snoop filter for a multi-processor system has a storage device and a control circuit. The control circuit manages at least a first-type entry and at least a second-type entry stored in the storage device. The first-type entry is configured to record information indicative of a first cache of the multi-processor system and first requested memory addresses that are associated with multiple first cache lines each being only available in the first cache. The second-type entry is configured to record information indicative of multiple second caches of the multi-processor system and at least a second requested memory address that is associated with a second cache line being available in each of the multiple second caches.

Abstract translation: 用于多处理器系统的窥探滤波器具有存储装置和控制电路。 控制电路管理存储在存储装置中的至少第一类型条目和至少第二类型条目。 第一类型条目被配置为记录指示多处理器系统的第一高速缓存的信息和与多个第一高速缓存行相关联的第一请求存储器地址，每个第一高速缓存行仅在第一高速缓存中可用。 第二类型条目被配置为记录指示多处理器系统的多个第二高速缓存的信息，以及与第二高速缓存行相关联的至少第二请求存储器地址在多个第二高速缓存中的每一个中可用。