公开(公告)号：US11451491B2

公开(公告)日：2022-09-20

申请号：US16704947

申请日：2019-12-05

Applicant: Juniper Networks, Inc.

Inventor： Pradeep Sindhu ,  Gunes Aybay ,  Jean-Marc Frailong ,  Anjan Venkatramani ,  Quaizar Vohra

IPC: H04L49/1515 ,  H04L49/35 ,  H04L49/00 ,  H04L49/25 ,  H04L49/356

Abstract: In one embodiment, an apparatus includes a switch core that has a multi-stage switch fabric. A first set of peripheral processing devices coupled to the multi-stage switch fabric by a set of connections that have a protocol. Each peripheral processing device from the first set of peripheral processing devices is a storage node that has virtualized resources. The virtualized resources of the first set of peripheral processing devices collectively define a virtual storage resource interconnected by the switch core. A second set of peripheral processing devices coupled to the multi-stage switch fabric by a set of connections that have the protocol. Each peripheral processing device from the first set of peripheral processing devices is a compute node that has virtualized resources. The virtualized resources of the second set of peripheral processing devices collectively define a virtual compute resource interconnected by the switch core.

公开(公告)号：US10887119B2

公开(公告)日：2021-01-05

申请号：US15799592

申请日：2017-10-31

Applicant: Juniper Networks, Inc.

Inventor： Sreekanth Reddy ,  Ravi Shekhar ,  Jeelani Syed ,  Quaizar Vohra

IPC: H04L12/00 ,  H04L12/18 ,  H04L12/931 ,  H04L12/46

Abstract: In some embodiments, a non-transitory processor-readable medium stores code representing instructions configured to cause a processor to receive, from an access switch, a first signal including forwarding state information associated with a first peripheral processing device from a set of peripheral processing devices. The code can further represent instructions configured to cause the processor to receive, from the first peripheral processing device, a second signal including a data packet. The code can further represent instructions configured to cause the processor to send, to a replication engine associated with the set of peripheral processing devices, a third signal such that the replication engine (1) defines a copy of the data packet, which is included within the third signal, and (2) sends, to a second peripheral processing device from the set of peripheral processing devices, a fourth signal including the copy of the data packet.

公开(公告)号：US10454849B2

公开(公告)日：2019-10-22

申请号：US15990102

申请日：2018-05-25

Applicant: Juniper Networks, Inc.

Inventor： Pradeep Sindhu ,  Gunes Aybay ,  Jean-Marc Frailong ,  Anjan Venkatramani ,  Quaizar Vohra

IPC: H04L12/28 ,  H04L12/931 ,  H04L12/935 ,  H04L12/24 ,  H04L12/947 ,  H04L29/06

Abstract: In one embodiment, edge devices can be configured to be coupled to a multi-stage switch fabric and peripheral processing devices. The edge devices and the multi-stage switch fabric can collectively define a single logical entity. A first edge device from the edge devices can be configured to be coupled to a first peripheral processing device from the peripheral processing devices. The second edge device from the edge devices can be configured to be coupled to a second peripheral processing device from the peripheral processing devices. The first edge device can be configured such that virtual resources including a first virtual resource can be defined at the first peripheral processing device. A network management module coupled to the edge devices and configured to provision the virtual resources such that the first virtual resource can be migrated from the first peripheral processing device to the second peripheral processing device.

公开(公告)号：US20150163171A1

公开(公告)日：2015-06-11

申请号：US14621892

申请日：2015-02-13

Applicant: Juniper Networks, Inc.

Inventor： Pradeep Sindhu ,  Gunes Aybay ,  Jean-Marc Frailong ,  Anjan Venkatramani ,  Quaizar Vohra

IPC: H04L12/935

CPC classification number: H04L49/30 ,  H04L41/0806 ,  H04L41/0846 ,  H04L49/257 ,  H04L49/35 ,  H04L49/356 ,  H04L63/101

Abstract: In one embodiment, edge devices can be configured to be coupled to a multi-stage switch fabric and peripheral processing devices. The edge devices and the multi-stage switch fabric can collectively define a single logical entity. A first edge device from the edge devices can be configured to be coupled to a first peripheral processing device from the peripheral processing devices. The second edge device from the edge devices can be configured to be coupled to a second peripheral processing device from the peripheral processing devices. The first edge device can be configured such that virtual resources including a first virtual resource can be defined at the first peripheral processing device. A network management module coupled to the edge devices and configured to provision the virtual resources such that the first virtual resource can be migrated from the first peripheral processing device to the second peripheral processing device.

Abstract translation: 在一个实施例中，边缘设备可被配置为耦合到多级交换结构和外围处理设备。 边缘设备和多级交换结构可以共同定义单个逻辑实体。 来自边缘设备的第一边缘设备可以被配置为从外围处理设备耦合到第一外围处理设备。 来自边缘设备的第二边缘设备可以被配置为从外围处理设备耦合到第二外围处理设备。 第一边缘设备可以被配置为使得可以在第一外围处理设备处定义包括第一虚拟资源的虚拟资源。 网络管理模块，其耦合到所述边缘设备并且被配置为提供所述虚拟资源，使得所述第一虚拟资源可以从所述第一外围处理设备迁移到所述第二外围处理设备。