公开(公告)号：US20180278547A1

公开(公告)日：2018-09-27

申请号：US15990102

申请日：2018-05-25

Applicant: Juniper Networks, Inc.

Inventor： Pradeep SINDHU ,  Gunes AYBAY ,  Jean-Marc FRAILONG ,  Anjan VENKATRAMANI ,  Quaizar VOHRA

IPC: H04L12/935 ,  H04L12/931 ,  H04L12/24 ,  H04L12/947 ,  H04L29/06

CPC classification number: H04L49/30 ,  H04L41/0806 ,  H04L41/0846 ,  H04L49/257 ,  H04L49/35 ,  H04L49/356 ,  H04L63/101 ,  Y02D30/30

Abstract: In one embodiment, edge devices can be configured to be coupled to a multi-stage switch fabric and peripheral processing devices. The edge devices and the multi-stage switch fabric can collectively define a single logical entity. A first edge device from the edge devices can be configured to be coupled to a first peripheral processing device from the peripheral processing devices. The second edge device from the edge devices can be configured to be coupled to a second peripheral processing device from the peripheral processing devices. The first edge device can be configured such that virtual resources including a first virtual resource can be defined at the first peripheral processing device. A network management module coupled to the edge devices and configured to provision the virtual resources such that the first virtual resource can be migrated from the first peripheral processing device to the second peripheral processing device.

公开(公告)号：US20140348170A1

公开(公告)日：2014-11-27

申请号：US14454338

申请日：2014-08-07

Applicant: JUNIPER NETWORKS, INC.

Inventor： Yafan AN ,  Sandeep KUMAR ,  Gunes AYBAY ,  Rakesh DUBEY

IPC: H04W28/02 ,  H04L12/723 ,  H04L29/12

CPC classification number: H04L45/124 ,  H04L45/02 ,  H04L45/025 ,  H04L45/08 ,  H04L45/12 ,  H04L45/127 ,  H04L45/22 ,  H04L45/50 ,  H04L45/54 ,  H04L45/745 ,  H04L45/7453 ,  H04L61/10 ,  H04L61/103 ,  H04L67/1072 ,  H04W28/0278

Abstract: A node is configured to receive a packet from a host device, where the packet includes a source address associated with the host device; determine that the source address is not stored by the node; generate one or more logical distances, associated with one or more nodes, based on the source address and a respective address associated with each of the nodes; determine that another node is associated with a shortest logical distance, of the one or more logical distances; and transmit the source address to the other node based on the determination that the other node is associated with the shortest logical distance, where transmitting the source address allows the other node to store the source address or enables further nodes to obtain the source address from the other node.

Abstract translation: 节点被配置为从主机设备接收分组，其中分组包括与主机设备相关联的源地址; 确定源地址不是由节点存储的; 基于源地址和与每个节点相关联的相应地址生成与一个或多个节点相关联的一个或多个逻辑距离; 确定另一个节点与一个或多个逻辑距离的最短逻辑距离相关联; 并且基于其他节点与最短逻辑距离相关联的确定将源地址发送到另一节点，其中发送源地址允许其他节点存储源地址或使得其他节点能够从源地址获得源地址 其他节点。