公开(公告)号：US20070014184A1

公开(公告)日：2007-01-18

申请号：US11383064

申请日：2006-05-12

Applicant: Ho-Kil LEE ,  Jin-Yub LEE

Inventor： Ho-Kil LEE ,  Jin-Yub LEE

IPC: G11C8/00

CPC classification number: G11C8/08 ,  G11C16/0483 ,  G11C16/08

Abstract: A wordline decoder for a non-volatile memory device includes a first inverter to invert a block selection signal into a first inverted result on a first node, a second inverter to invert the signal on the first node into a second inverted result on a second node, a first and a second transistor, each coupled to a power supply, coupled in series between the second node and a third node, a third transistor coupled between the third node and a fourth node having a gate coupled to the third node, a fourth transistor coupled between a high voltage supply and a fifth node having a source coupled to the high voltage supply and a gate coupled to the third node, and a fifth transistor coupled between the fifth node and the third node having a gate coupled to the first node.

Abstract translation: 用于非易失性存储器件的字线解码器包括：第一反相器，用于将块选择信号反转到第一节点上的第一反相结果;第二反相器，用于将第一节点上的信号反转为第二节点上的第二反相结果 ，第一和第二晶体管，每个耦合到电源，串联耦合在第二节点和第三节点之间;第三晶体管，耦合在第三节点和第四节点之间，第四节点具有耦合到第三节点的栅极;第四晶体管，第四晶体管， 耦合在高压电源和耦合到高压电源的源极的第五节点和耦合到第三节点的栅极之间的晶体管，以及耦合在第五节点和第三节点之间的第五晶体管，其具有耦合到第一节点 。