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11.发明授权公开(公告)号：US11537403B2
公开(公告)日：2022-12-27
申请号：US17213453
申请日：2021-03-26
Applicant: Intel Corporation
Inventor： Subramaniam M. Maiyuran , Guei-Yuan Lueh , Supratim Pal , Gang Chen , Ananda V. Kommaraju , Joy Chandra , Altug Koker , Prasoonkumar Surti , David Puffer , Hong Bin Liao , Joydeep Ray , Abhishek R. Appu , Ankur N. Shah , Travis T. Schluessler , Jonathan Kennedy , Devan Burke
Abstract: An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.
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公开(公告)号：US11508338B2
公开(公告)日：2022-11-22
申请号：US17062871
申请日：2020-10-05
Applicant: Intel Corporation
Inventor： Joydeep Ray , Altug Koker , Balaji Vembu , Murali Ramadoss , Guei-Yuan Lueh , James A. Valerio , Prasoonkumar Surti , Abhishek R. Appu , Vasanth Ranganathan , Kalyan K. Bhiravabhatla , Arthur D. Hunter, Jr. , Wei-Yu Chen , Subramaniam M. Maiyuran
IPC: G09G5/36 , G06F12/0875 , G06F9/46 , G09G5/00 , G06F12/084 , G06F12/0811
Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.
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公开(公告)号：US11354768B2
公开(公告)日：2022-06-07
申请号：US16791482
申请日：2020-02-14
Applicant: Intel Corporation
Inventor： Balaji Vembu , Murali Ramadoss , Guei-Yuan Lueh , Subramaniam M. Maiyuran , Abhishek R. Appu , Joydeep Ray , Altug Koker , James A. Valerio , Eric J. Hoekstra , Arthur D. Hunter, Jr.
Abstract: An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.
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公开(公告)号：US10796667B2
公开(公告)日：2020-10-06
申请号：US16599175
申请日：2019-10-11
Applicant: Intel Corporation
Inventor： Joydeep Ray , Altug Koker , Balaji Vembu , Murali Ramadoss , Guei-Yuan Lueh , James A. Valerio , Prasoonkumar Surti , Abhishek R. Appu , Vasanth Ranganathan , Kalyan K. Bhiravabhatla , Arthur D. Hunter, Jr. , Wei-Yu Chen , Subramaniam M. Maiyuran
IPC: G09G5/36 , G06F12/0875 , G06F9/46 , G09G5/00 , G06F12/084 , G06F12/0811
Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.
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公开(公告)号：US10725785B2
公开(公告)日：2020-07-28
申请号：US16503944
申请日：2019-07-05
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Abhishek R. Appu , Joydeep Ray , Subramaniam M. Maiyuran , Altug Koker
IPC: G06F12/06 , G06F12/0875 , G06T1/20 , G06T1/60 , G06T15/00 , G09G5/393 , H04N19/423 , H04N19/436 , G06F9/30 , G06F9/38 , G06F9/50 , G06F8/41
Abstract: An apparatus to facilitate memory tiling is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads via access to the memory and tiling logic to apply a tiling pattern to memory addresses for data stored in the memory.
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公开(公告)号：US20190251652A1
公开(公告)日：2019-08-15
申请号：US16252379
申请日：2019-01-18
Applicant: Intel Corporation
Inventor： Balaji Vernbu , Murali Rarnadoss , Guei-Yuan Lueh , Subramaniam M. Maiyuran , Abhishek R. Appu , Joydeep Ray , Altug Koker , James A. Valerio , Eric J. Hoekstra , Arthur D. Hunter, JR.
Abstract: An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.
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公开(公告)号：US10235736B2
公开(公告)日：2019-03-19
申请号：US15493420
申请日：2017-04-21
Applicant: Intel Corporation
Inventor： Balaji Vembu , Murali Ramadoss , Guei-Yuan Lueh , Subramaniam M. Maiyuran , Abhishek R. Appu , Joydeep Ray , Altug Koker , James A. Valerio , Eric J. Hoekstra , Arthur D. Hunter, Jr.
Abstract: An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.
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公开(公告)号：US20180300845A1
公开(公告)日：2018-10-18
申请号：US15488547
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Adam T. Lake , Guei-Yuan Lueh , Balaji Vembu , Murali Ramadoss , Prasoonkumar Surti , Abhishek R. Appu , Altug Koker , Subramaniam M. Maiyuran , Eric C. Samson , David J. Cowperthwaite , Zhi Wang , Kun Tian , David Puffer , Brian T. Lewis
Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.
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公开(公告)号：US12067641B2
公开(公告)日：2024-08-20
申请号：US17749266
申请日：2022-05-20
Applicant: Intel Corporation
Inventor： Altug Koker , Ingo Wald , David Puffer , Subramaniam M. Maiyuran , Prasoonkumar Surti , Balaji Vembu , Guei-Yuan Lueh , Murali Ramadoss , Abhishek R. Appu , Joydeep Ray
CPC classification number: G06T1/20 , G06F9/3009 , G06F9/30185 , G06F9/3851 , G06F9/461 , G06F9/4843
Abstract: One embodiment provides a parallel processor comprising a memory interface and a processing array coupled with the memory interface. The processing array is configured to address memory accessed via the memory interface via a virtual address mapping and includes circuitry to resolve a page fault for the virtual address mapping, wherein each of the multiple compute blocks is separately preemptable.
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公开(公告)号：US11715174B2
公开(公告)日：2023-08-01
申请号：US17685445
申请日：2022-03-03
Applicant: Intel Corporation
Inventor： Murali Ramadoss , Balaji Vembu , Eric C. Samson , Kun Tian , David J. Cowperthwaite , Altug Koker , Zhi Wang , Joydeep Ray , Subramaniam M. Maiyuran , Abhishek R. Appu
CPC classification number: G06T1/20 , G06F9/3887 , G06F9/4806 , G06F9/4843 , G06F9/4881 , G06F9/5083 , G06F9/5088 , G06F11/0793 , G06F2209/5017 , G06T2200/28 , G06T2210/52 , Y02D10/00
Abstract: Embodiments described herein provide techniques enable a graphics processor to continue processing operations during the reset of a compute unit that has experienced a hardware fault. Threads and associated context state for a faulted compute unit can be migrated to another compute unit of the graphics processor and the faulting compute unit can be reset while processing operations continue.
