公开(公告)号：US20160188499A1

公开(公告)日：2016-06-30

申请号：US14583156

申请日：2014-12-25

Applicant: Intel Corporation

Inventor： Ramadass Nagarajan ,  Michael T. Klinglesmith ,  Joydeep Ray

IPC: G06F13/16 ,  G06F15/78

CPC classification number: G06F13/1615 ,  G06F13/1663 ,  G06F15/7821 ,  Y02D10/14

Abstract: Selected portions of an uncore fabric of a system-on-a-chip (SoC) or other embedded system are divided into two independent pipelines. Each pipeline operates independently of the other pipeline, and each accesses only one-half of the system memory, such as even or odd addresses in an interleaved memory. However, the two pipelines are tightly coupled to maintain coherency of the fabric. Coupling may be accomplished, for example, by a shared clock that is one-half of the base clock cycle for the fabric. Each incoming address may be processed by a deterministic hash, assigned to one of the pipelines, processed through memory, and then passed to a credit return.

Abstract translation: 系统级芯片（SoC）或其他嵌入式系统的非空心结构的选定部分被划分为两条独立的管道。 每个流水线独立于其他流水线运行，并且每个流水线仅访问系统存储器的一半，例如交错存储器中的偶数或奇数地址。 然而，两个管道紧密耦合以保持织物的一致性。 耦合可以例如通过共享时钟来实现，该共享时钟是针对结构的基本时钟周期的一半。 每个传入地址可以通过确定性散列来处理，分配给其中一条管道，通过存储器处理，然后传递给信用回报。

公开(公告)号：US20150019788A1

公开(公告)日：2015-01-15

申请号：US14497567

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Robert P. Adler ,  Eran Tamari ,  Mikal C. Hunsaker ,  Sridhar Lakshmanamurthy ,  Michael T. Klinglesmith ,  Blaise Fanning

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/366 ,  G06F13/4036

Abstract: According to one embodiment, a system on a chip includes multiple agents each corresponding to an intellectual property (IP) logic and a fabric to couple the agents. The fabric can include a primary message interface and a sideband message interface. The fabric further includes one or more routers to provide out-of-band communications between the agents via this sideband message interface. To effect such communication, the router can perform a subset of ordering rules of a personal computer (PC)-based specification for sideband messages. Other embodiments are described and claimed.

Abstract translation: 根据一个实施例，芯片上的系统包括每个对应于知识产权（IP）逻辑的多个代理和用于耦合代理的结构。 该结构可以包括主消息接口和边带消息接口。 该结构还包括一个或多个路由器，以经由该边带消息接口在代理之间提供带外通信。 为了实现这种通信，路由器可以执行用于边带消息的基于个人计算机（PC）的规范的排序规则的子集。 描述和要求保护其他实施例。

公开(公告)号：US10754808B2

公开(公告)日：2020-08-25

申请号：US15572436

申请日：2015-12-20

Applicant: Intel Corporation

Inventor： Prashant Sethi ,  Michael T. Klinglesmith ,  David J. Harriman ,  Reuven Rozic ,  Shanthanand Kutuva Rabindrananth

IPC: G06F13/40 ,  G06F13/42 ,  G06F12/1081 ,  G06F12/1009 ,  G06F12/1027

Abstract: Bridge logic is provided to receive a request from a device, where the request references an address of a secondary address space. The secondary address space corresponds to a subset of addresses in a configuration address space of a system, and the secondary address space corresponds to a first view of the configuration address space. The bridge logic uses a mapping table to translate the address into a corresponding address in the configuration address space, where addresses of the configuration address space correspond to a different second view of the configuration address space.

公开(公告)号：US20190311960A1

公开(公告)日：2019-10-10

申请号：US15948851

申请日：2018-04-09

Applicant: Intel Corporation

Inventor： Terrence Huat Hin Tan ,  Rehan Sheikh ,  Michael T. Klinglesmith ,  Sukhbinder Takhar ,  Shi Hou Chong ,  Kok Hin Oon ,  Wai Loon Yip ,  Yudhishthira Kundu ,  Deepak R. Tanna

IPC: H01L21/66 ,  H01L25/065 ,  H01L23/498 ,  G01R31/28

Abstract: Disclosed herein are structures and techniques for exposing circuitry in die testing. For example, in some embodiments, an integrated circuit (IC) die may include: first conductive contacts at a first face of the die; second conductive contacts at a second face of the die; die stack emulation circuitry; other circuitry; and a switch coupled to the second conductive contacts, the die stack emulation circuitry, and the other circuitry, wherein the switch is to couple the second conductive contacts to the other circuitry when the switch is in a first state, and the switch is to couple the die stack emulation circuitry to the other circuitry when the switch is in a second state different from the first state.

公开(公告)号：US10157160B2

公开(公告)日：2018-12-18

申请号：US14865005

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Michael T. Klinglesmith ,  Mikal C. Hunsaker ,  William Knolla ,  Hartej Singh

IPC: G06F13/00 ,  G06F13/14 ,  G06F3/00 ,  G06F13/42 ,  G06F13/20 ,  G06F13/40

Abstract: In one embodiment, a method includes: receiving, via a sideband interface of a multi-root agent associated with a first root space and a second root space, a reset prepare signal to inform the multi-root agent that the first root space is to be reset; sending, via the sideband interface, an acknowledgement signal to acknowledge the reset prepare signal; receiving one or more transactions for the first root space from a fabric coupled to the multi-root agent; and terminating the one or more transactions responsive to the reset prepare signal, where the first root space is in a reset state when the one or more transactions are received. Other embodiments are described and claimed.

公开(公告)号：US09990327B2

公开(公告)日：2018-06-05

申请号：US14880443

申请日：2015-10-12

Applicant: Intel Corporation

Inventor： Michael T. Klinglesmith ,  Chang Yong Kang ,  Robert DeGruijl ,  Ioannis T. Schoinas ,  Darren Abramson ,  Khee Wooi Lee

IPC: G06F13/14 ,  G06F13/42 ,  G06F3/06 ,  G06F12/0817 ,  G06F13/16

CPC classification number: G06F13/4282 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/068 ,  G06F12/0828 ,  G06F13/1663 ,  G06F2212/621

Abstract: In one embodiment, a system includes: a first root space associated with a first root space identifier and including at least one first host processor and a first agent, the at least one first host processor and the first agent associated with the first root space identifier; a second root space associated with a second root space identifier and including at least one second host processor and a second agent, the at least one second host processor and the second agent associated with the second root space identifier; and a shared fabric to couple the first root space and the second root space, the shared fabric to route a transaction to the first root space or the second root space based at least in part on a root space field of the transaction. Other embodiments are described and claimed.

公开(公告)号：US09971711B2

公开(公告)日：2018-05-15

申请号：US14583156

申请日：2014-12-25

Applicant: Intel Corporation

Inventor： Ramadass Nagarajan ,  Michael T. Klinglesmith ,  Joydeep Ray

IPC: G06F13/16 ,  G06F15/78

CPC classification number: G06F13/1615 ,  G06F13/1663 ,  G06F15/7821 ,  Y02D10/14

Abstract: Selected portions of an uncore fabric of a system-on-a-chip (SoC) or other embedded system are divided into two independent pipelines. Each pipeline operates independently of the other pipeline, and each accesses only one-half of the system memory, such as even or odd addresses in an interleaved memory. However, the two pipelines are tightly coupled to maintain coherency of the fabric. Coupling may be accomplished, for example, by a shared clock that is one-half of the base clock cycle for the fabric. Each incoming address may be processed by a deterministic hash, assigned to one of the pipelines, processed through memory, and then passed to a credit return.

公开(公告)号：US09064051B2

公开(公告)日：2015-06-23

申请号：US14295810

申请日：2014-06-04

Applicant: Intel Corporation

Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Eran Tamari ,  Joseph Murray ,  Kar Leong Wong ,  Robert P. Adler

IPC: G06F3/00 ,  G06F5/00 ,  G06F13/366 ,  G06F15/78 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/366 ,  G06F13/368 ,  G06F13/4022 ,  G06F15/7807 ,  G06F15/7864

Abstract: In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，一种方法包括确定是否已经通过结构从源代理发送到目标代理的第一事务已经满足生产者 - 消费者排序规则，并且如果是，则从第一事务发送第一事务的第一请求 源代理程序在第一个时钟周期。 然后，可以以流水线的方式从源代理向结构发送第二请求用于第二事务。 描述和要求保护其他实施例。

公开(公告)号：US20150113189A1

公开(公告)日：2015-04-23

申请号：US14578720

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Eran Tamari ,  Joseph Murray ,  Kar Leong Wong ,  Robert P. Adler

IPC: G06F13/42 ,  G06F13/368

CPC classification number: G06F13/4221 ,  G06F13/366 ,  G06F13/368 ,  G06F13/4022 ,  G06F15/7807 ,  G06F15/7864

Abstract: In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，一种方法包括确定是否已经通过结构从源代理发送到目标代理的第一事务已经满足生产者 - 消费者排序规则，并且如果是，则从第一事务发送第一事务的第一请求 源代理程序在第一个时钟周期。 然后，可以以流水线的方式从源代理向结构发送第二请求用于第二事务。 描述和要求保护其他实施例。

公开(公告)号：US11476168B2

公开(公告)日：2022-10-18

申请号：US15948851

申请日：2018-04-09

Applicant: Intel Corporation

Inventor： Terrence Huat Hin Tan ,  Rehan Sheikh ,  Michael T. Klinglesmith ,  Sukhbinder Takhar ,  Shi Hou Chong ,  Kok Hin Oon ,  Wai Loon Yip ,  Yudhishthira Kundu ,  Deepak R. Tanna

IPC: H01L21/66 ,  H01L25/065 ,  H01L23/498 ,  G01R31/28

Abstract: Disclosed herein are structures and techniques for exposing circuitry in die testing. For example, in some embodiments, an integrated circuit (IC) die may include: first conductive contacts at a first face of the die; second conductive contacts at a second face of the die; die stack emulation circuitry; other circuitry; and a switch coupled to the second conductive contacts, the die stack emulation circuitry, and the other circuitry, wherein the switch is to couple the second conductive contacts to the other circuitry when the switch is in a first state, and the switch is to couple the die stack emulation circuitry to the other circuitry when the switch is in a second state different from the first state.