公开(公告)号：US20210074620A1

公开(公告)日：2021-03-11

申请号：US16564168

申请日：2019-09-09

Applicant: Intel Corporation

Inventor： Johanna Swan ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong

IPC: H01L23/498 ,  G03F1/54 ,  G03F1/68 ,  G03F1/38

Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.

公开(公告)号：US20240264530A1

公开(公告)日：2024-08-08

申请号：US18147472

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Ryan Carrazzone ,  Kyle Arrington ,  Brandon Rawlings ,  Bohan Shan ,  Dingying Xu

IPC: G03F7/16 ,  C08G75/20 ,  G03F7/038 ,  G03F7/039

CPC classification number: G03F7/168 ,  C08G75/20 ,  G03F7/038 ,  G03F7/039

Abstract: Light responsive photoresists, and methods of using light responsive photoresists in processes, such as lithography processes. The light responsive photoresists may include a polymer featuring a photocleavable group. Due to the photocleavable group, the polymer may depolymerize when irradiated with one or more wavelengths of light. The depolymerized products may be in the gas phase.

公开(公告)号：US20230198058A1

公开(公告)日：2023-06-22

申请号：US17556784

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Veronica Strong ,  Telesphor Kamgaing ,  Neelam Prabhu Gaunkar ,  Georgios Dogiamis ,  Aleksandar Aleksov ,  Brandon Rawlings

IPC: H01M50/117 ,  H01L23/58

CPC classification number: H01M50/117 ,  H01L23/58

Abstract: Embedded batteries within glass cores are disclosed. Example apparatus include a glass core layer having opposing first and second surfaces, the glass core layer including a cavity extending from the first surface toward the second surface, and a battery including a first conductive material positioned in the cavity, a second conductive material positioned in the cavity, and an electrolyte to separate the first conductive material from the second conductive material.

公开(公告)号：US20210343635A1

公开(公告)日：2021-11-04

申请号：US17375360

申请日：2021-07-14

Applicant: Intel Corporation

Inventor： Johanna Swan ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong

IPC: H01L23/498 ,  G03F1/38 ,  G03F1/54 ,  G03F1/68

Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.

公开(公告)号：US11664303B2

公开(公告)日：2023-05-30

申请号：US17375360

申请日：2021-07-14

Applicant: Intel Corporation

Inventor： Johanna Swan ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong

IPC: H01L23/498 ,  G03F1/38 ,  G03F1/54 ,  G03F1/68

CPC classification number: H01L23/49838 ,  G03F1/38 ,  G03F1/54 ,  G03F1/68 ,  H01L23/49827 ,  H01L23/49866

Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.

公开(公告)号：US11460499B2

公开(公告)日：2022-10-04

申请号：US16573946

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Aleksandar Aleksov ,  Veronica Strong ,  Brandon Rawlings ,  Johanna Swan ,  Shawna Liff

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  G01R31/28 ,  G01K7/42 ,  G01K7/02

Abstract: An integrated circuit package having an electronic interposer comprising an upper section, a lower section and a middle section, a die side integrated circuit device electrically attached to the upper section of the electronic interposer, a die side heat dissipation device thermally contacting the die side integrated circuit device, a land side integrated circuit device electrically attached to the lower section of the electronic interposer, and a land side heat dissipation device thermally contacting the at least one die side integrated circuit device. The upper section and the lower section may each have between two and four layers and the middle section may be formed between the upper section and the lower section, and comprises up to eight layers, wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and the lower section.

公开(公告)号：US11328996B2

公开(公告)日：2022-05-10

申请号：US16648640

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Veronica Strong ,  Aleksandar Aleksov ,  Brandon Rawlings

IPC: H01L23/538 ,  H01L23/522 ,  H01L23/00

Abstract: A device package and method of forming the device package are described. The device package includes a dielectric on a conductive pad, a first via on a top surface of conductive pad, where the first via extends through dielectric, and a conductive trace on dielectric. The device package has a second via on dielectric, where the conductive trace connects to first and second vias, and the second via connects to an edge of conductive trace opposite from first via. The device package may have a seed on dielectric, where the seed electrically couples to conductive trace, a first seed on the top surface of conductive pad, where the first via is on first seed, and a second seed on a top surface of first via, the second seed on surfaces of second via, where the conductive trace is on second seed disposed on both first and second vias.

公开(公告)号：US11222836B2

公开(公告)日：2022-01-11

申请号：US16649578

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Veronica Strong ,  Aleksandar Aleksov ,  Brandon Rawlings ,  Johanna Swan

IPC: H01L29/40 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L23/538

Abstract: Device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS directly coupled to the interconnect. The ZM2VS further includes the dielectric on a conductive pad, a first via on a first seed, and first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS also has a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.

公开(公告)号：US20210082822A1

公开(公告)日：2021-03-18

申请号：US16573943

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Henning Braunisch ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong ,  Johanna Swan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498

Abstract: An electronic interposer may be formed comprising an upper section, a lower section and a middle section. The upper section and the lower section may each have between two and four layers, wherein each layer comprises an organic material layer and at least one conductive route comprising at least one conductive trace and at least one conductive via. The middle section may be formed between the upper section and the lower section, wherein the middle section comprises up to eight layers, wherein each layer comprises an organic material and at least one conductive route comprising at least one conductive trace and at least one conductive via, and wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and thinner than a thickness of any of the layers of the lower section.