公开(公告)号：US20170076970A1

公开(公告)日：2017-03-16

申请号：US15359620

申请日：2016-11-23

Applicant: Infineon Technologies AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Rainer Leuschner ,  Bernhard Goller ,  Bernhard Boche ,  Manfred Engelhardt ,  Hermann Wendt ,  Bernd Noehammer ,  Karl Mayer ,  Michael Roesner ,  Monika Cornelia Voerckel

IPC: H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L21/285 ,  H01L21/304 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/6835 ,  H01L21/0331 ,  H01L21/283 ,  H01L21/2855 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/6836 ,  H01L21/76895 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/0001

Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.

Abstract translation: 用于处理半导体工件的方法可以包括提供包括一个或多个切口区域的半导体工件; 通过从所述工件的第一侧移除来自所述一个或多个切割区域的材料，在所述工件中形成一个或多个沟槽; 将具有第一侧的工件安装到载体上; 从工件的第二侧使工件变薄; 以及在所述工件的第二侧上形成金属化层。

公开(公告)号：US20150368097A1

公开(公告)日：2015-12-24

申请号：US14838988

申请日：2015-08-28

Applicant: Infineon Technologies AG

Inventor： Andreas Behrendt ,  Kai-Alexander Schreiber ,  Sokratis Sgouridis ,  Martin Zgaga ,  Bernhard Winkler

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00531 ,  B81B3/0021 ,  B81B3/0094 ,  B81B2203/033 ,  B81C1/00619 ,  B81C1/00626 ,  B81C2201/0139 ,  H01L21/3063

Abstract: A method for producing at least one cavity within a semiconductor substrate includes dry etching the semiconductor substrate from a surface of the semiconductor substrate at at least one intended cavity location in order to obtain at least one provisional cavity. The method includes depositing a protective material with regard to a subsequent wet-etching process at the surface of the semiconductor substrate and at cavity surfaces of the at least one provisional cavity. Furthermore, the method includes removing the protective material at least at a section of a bottom of the at least one provisional cavity in order to expose the semiconductor substrate. This is followed by electrochemically etching the semiconductor substrate at the exposed section of the bottom of the at least one provisional cavity. A method for producing a micromechanical sensor system in which this type of cavity formation is used and a corresponding MEMS are also disclosed.

Abstract translation: 一种用于在半导体衬底内制造至少一个空腔的方法包括：在半导体衬底的表面在至少一个预定的腔位置干蚀刻半导体衬底，以便获得至少一个临时空腔。 该方法包括在半导体衬底的表面和至少一个临时空腔的空腔表面处沉积关于随后的湿法蚀刻工艺的保护材料。 此外，该方法包括至少在至少一个临时空腔的底部的一部分处去除保护材料以暴露半导体衬底。 接着在至少一个临时腔的底部的暴露部分对半导体衬底进行电化学蚀刻。 还公开了使用这种类型的空腔形成和相应的MEMS的微机械传感器系统的制造方法。

公开(公告)号：US20130270658A1

公开(公告)日：2013-10-17

申请号：US13864762

申请日：2013-04-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Andreas Behrendt ,  Kai-Alexander Schreiber ,  Sokratis Sgouridis ,  Martin Zgaga ,  Bernhard Winkler

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00531 ,  B81B3/0021 ,  B81B3/0094 ,  B81B2203/033 ,  B81C1/00619 ,  B81C1/00626 ,  B81C2201/0139 ,  H01L21/3063

Abstract: A method for producing at least one cavity within a semiconductor substrate includes dry etching the semiconductor substrate from a surface of the semiconductor substrate at at least one intended cavity location in order to obtain at least one provisional cavity. The method includes depositing a protective material with regard to a subsequent wet-etching process at the surface of the semiconductor substrate and at cavity surfaces of the at least one provisional cavity. Furthermore, the method includes removing the protective material at least at a section of a bottom of the at least one provisional cavity in order to expose the semiconductor substrate. This is followed by electrochemically etching the semiconductor substrate at the exposed section of the bottom of the at least one provisional cavity. A method for producing a micromechanical sensor system in which this type of cavity formation is used and a corresponding MEMS are also disclosed.

公开(公告)号：US10672716B2

公开(公告)日：2020-06-02

申请号：US16029934

申请日：2018-07-09

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Gudrun Stranzl ,  Manfred Engelhardt ,  Martin Zgaga

IPC: H01L23/544 ,  H01L21/78 ,  H01L21/3065

Abstract: An integrated circuit substrate and a method for manufacturing the same are disclosed. In an embodiment a method includes providing a wafer having a plurality of active areas, each active area being provided in a separate die area and for each active area, providing a code pattern outside the active area, the code pattern being associated with the die area.

公开(公告)号：US09481563B2

公开(公告)日：2016-11-01

申请号：US14644937

申请日：2015-03-11

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Martin Zgaga

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/001 ,  B81B3/0051 ,  B81C1/00531 ,  B81C1/00626 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L21/30655

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a micro-mechanical structure and a semiconductor material arranged over the micro-mechanical structure. A side surface of the semiconductor material includes a first region and a second region. The first region has an undulation, and the second region is a peripheral region of the side surface and decreases towards the micro-mechanical structure.

Abstract translation: 根据半导体器件的实施例，半导体器件包括布置在微机械结构上的微机械结构和半导体材料。 半导体材料的侧表面包括第一区域和第二区域。 第一区域具有起伏，第二区域是侧表面的周边区域，朝向微机械结构减小。

公开(公告)号：US09257342B2

公开(公告)日：2016-02-09

申请号：US14260903

申请日：2014-04-24

Applicant: Infineon Technologies AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Markus Kahn ,  Guenter Denifl

IPC: H01L21/82 ,  H01L21/78 ,  H01L21/8258 ,  H01L21/308

CPC classification number: H01L21/78 ,  H01L21/02115 ,  H01L21/0212 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/82 ,  H01L21/8258

Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.

Abstract translation: 在一个实施例中，形成半导体器件的方法包括在衬底中形成开口。 该方法包括在开口内形成虚拟填充材料并使衬底变薄以暴露虚拟填充材料。 去除虚拟填充材料。

公开(公告)号：US09139427B2

公开(公告)日：2015-09-22

申请号：US13864762

申请日：2013-04-17

Applicant: Infineon Technologies AG

Inventor： Andreas Behrendt ,  Kai-Alexander Schreiber ,  Sokratis Sgouridis ,  Martin Zgaga ,  Bernhard Winkler

IPC: H01L21/311 ,  B81C1/00 ,  B81B3/00 ,  H01L21/3063

CPC classification number: B81C1/00531 ,  B81B3/0021 ,  B81B3/0094 ,  B81B2203/033 ,  B81C1/00619 ,  B81C1/00626 ,  B81C2201/0139 ,  H01L21/3063

Abstract: A method for producing at least one cavity within a semiconductor substrate includes dry etching the semiconductor substrate from a surface of the semiconductor substrate at at least one intended cavity location in order to obtain at least one provisional cavity. The method includes depositing a protective material with regard to a subsequent wet-etching process at the surface of the semiconductor substrate and at cavity surfaces of the at least one provisional cavity. Furthermore, the method includes removing the protective material at least at a section of a bottom of the at least one provisional cavity in order to expose the semiconductor substrate. This is followed by electrochemically etching the semiconductor substrate at the exposed section of the bottom of the at least one provisional cavity. A method for producing a micromechanical sensor system in which this type of cavity formation is used and a corresponding MEMS are also disclosed.

Abstract translation: 一种用于在半导体衬底内制造至少一个空腔的方法包括：在半导体衬底的表面在至少一个预定的腔位置干蚀刻半导体衬底，以便获得至少一个临时空腔。 该方法包括在半导体衬底的表面和至少一个临时空腔的空腔表面处沉积关于随后的湿法蚀刻工艺的保护材料。 此外，该方法包括至少在至少一个临时空腔的底部的一部分处去除保护材料以暴露半导体衬底。 接着在至少一个临时腔的底部的暴露部分对半导体衬底进行电化学蚀刻。 还公开了使用这种类型的空腔形成和相应的MEMS的微机械传感器系统的制造方法。

公开(公告)号：US20150147850A1

公开(公告)日：2015-05-28

申请号：US14088523

申请日：2013-11-25

Applicant: Infineon Technologies AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Rainer Leuschner ,  Bernhard Goller ,  Bernhard Boche ,  Manfred Engelhardt ,  Hermann Wendt ,  Bernd Noehammer ,  Karl Mayer ,  Michael Roesner ,  Monika Cornelia Voerckel

IPC: H01L21/82 ,  H01L21/283 ,  H01L21/265 ,  H01L23/00

CPC classification number: H01L21/6835 ,  H01L21/0331 ,  H01L21/283 ,  H01L21/2855 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/6836 ,  H01L21/76895 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/0001

Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.

Abstract translation: 用于处理半导体工件的方法可以包括提供包括一个或多个切口区域的半导体工件; 通过从所述工件的第一侧移除来自所述一个或多个切割区域的材料，在所述工件中形成一个或多个沟槽; 将具有第一侧的工件安装到载体上; 从工件的第二侧使工件变薄; 以及在所述工件的第二侧上形成金属化层。

公开(公告)号：US20140291779A1

公开(公告)日：2014-10-02

申请号：US13851691

申请日：2013-03-27

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Martin Zgaga

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81B3/001 ,  B81B3/0051 ,  B81C1/00531 ,  B81C1/00626 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L21/30655

Abstract: A method includes a step of performing a time multiplexed etching process, wherein the last etching step of the time multiplexed etching process is of a first time duration. After performing the time multiplexed etching process, an etching step having a second time duration is performed, wherein the second time duration is greater than the first time duration.

Abstract translation: 一种方法包括执行时间复用蚀刻工艺的步骤，其中时间复用蚀刻工艺的最后一个蚀刻步骤是第一持续时间。 在执行时间复用蚀刻处理之后，执行具有第二持续时间的蚀刻步骤，其中第二持续时间大于第一持续时间。

公开(公告)号：US10157765B2

公开(公告)日：2018-12-18

申请号：US15359620

申请日：2016-11-23

Applicant: Infineon Technologies AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Rainer Leuschner ,  Bernhard Goller ,  Bernhard Boche ,  Manfred Engelhardt ,  Hermann Wendt ,  Bernd Noehammer ,  Karl Mayer ,  Michael Roesner ,  Monika Cornelia Voerckel

IPC: H01L23/498 ,  H01L21/683 ,  H01L21/283 ,  H01L21/78 ,  H01L21/033 ,  H01L21/285 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/768

Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.