知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

25 records (took 0.065 seconds)

    Method and apparatus for stacking core and uncore dies having landing slots
    14.
    发明授权
    Method and apparatus for stacking core and uncore dies having landing slots 有权
    用于堆叠具有着陆槽的芯和裸芯片的方法和装置

    公开(公告)号：US09514093B2

    公开(公告)日：2016-12-06

    申请号：US14498353

    申请日：2014-09-26

    Applicant: INTEL CORPORATION

    Inventor： Stefan Rusu

    IPC: G06F15/76 ,  H01L25/065

    CPC classification number: H01L25/18 ,  G06F12/1045 ,  G06F15/76 ,  G06F2212/1008 ,  G06F2212/283 ,  G06F2212/455 ,  G06F2212/608 ,  G06F2212/68 ,  H01L23/481 ,  H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An apparatus and method are described for stacking a plurality of cores. For example, one embodiment of an apparatus comprises: a package; an uncore die mounted on the package, the uncore die comprising a plurality of exposed landing slots, each landing slot including an inter-die interface usable to connect vertically to a cores die, the uncore die including a plurality of uncore components usable by cores within the cores die including a memory controller component, a level 3 (L3) cache, a system memory or system memory interface, and a core interconnect fabric or bus; and a first cores die comprising a first plurality of cores, the cores spaced on the first cores die to correspond to all or a first subset of the landing slots on the uncore die, each of the cores having an inter-die interface positioned to be communicatively coupled to a corresponding inter-die interface within a landing slot on the uncore die when the first cores die is vertically coupled on top of the uncore die, wherein the communicative coupling between the inter-die interface of a core and the inter-die interface of its corresponding landing slot communicatively couples the core to the uncore components of the uncore die.

    Abstract translation: 描述了用于堆叠多个核的装置和方法。 例如，装置的一个实施例包括：包装; 安装在所述封装上的非芯模，所述裸芯包括多个暴露的着陆槽，每个着陆槽包括可垂直地连接到芯模的管芯间界面，所述裸芯包括多个可由核心内部的芯部 核心包括存储器控制器组件，级别3（L3）高速缓存，系统存储器或系统存储器接口以及核心互连结构或总线; 以及包括第一多个芯的第一芯芯，所述芯在所述第一芯上分开，以对应于所述裸芯上的所述着陆槽的全部或第一子集，所述芯中的每一个具有定位成为 当所述第一芯管芯垂直耦合在所述裸芯片的顶部上时，在所述裸芯片上的着陆槽内通信地耦合到相应的晶片间界面，其中，所述芯体的晶片间界面与所述晶片间的交流耦合 其对应的着陆槽的接口将核心通信地耦合到裸芯片的非零部件。

    Adaptively controlling low power mode operation for a cache memory
    15.
    发明授权
    Adaptively controlling low power mode operation for a cache memory 有权
    自适应地控制高速缓冲存储器的低功耗模式操作

    公开(公告)号：US09335814B2

    公开(公告)日：2016-05-10

    申请号：US14012362

    申请日：2013-08-28

    Applicant: Intel Corporation

    Inventor： Stefan Rusu ,  Min Huang ,  Wei Chen ,  Krishnakanth V. Sistla

    IPC: G06F1/32 ,  G06F1/00 ,  G06F13/00

    CPC classification number: G06F1/3275 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

    Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a cache memory including a plurality of portions distributed across a die of the processor, a plurality of sleep circuits each coupled to one of the portions of the cache memory, and at least one sleep control logic coupled to the cache memory portions to dynamically determine a sleep setting independently for each of the sleep circuits and to enable the corresponding sleep circuit to maintain the corresponding cache memory portion at a retention voltage. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括多个核心，每个核心各自独立地执行指令;高速缓存存储器，包括分布在处理器的管芯上的多个部分;多个休眠电路，每个休眠电路分别耦合到高速缓冲存储器的一个部分， 以及耦合到所述高速缓存存储器部分的至少一个睡眠控制逻辑，以针对每个所述睡眠电路独立动态地确定睡眠设置，并且使所述相应的休眠电路能够将所述对应的高速缓冲存储器部分维持在保持电压。 描述和要求保护其他实施例。

    Converged Adaptive Compensation Scheme
    16.
    发明申请
    Converged Adaptive Compensation Scheme 有权
    融合自适应补偿方案

    公开(公告)号：US20160087918A1

    公开(公告)日：2016-03-24

    申请号：US14494190

    申请日：2014-09-23

    Applicant: Intel Corporation

    Inventor： Roger K. Cheng ,  Stefan Rusu ,  Aaron Martin

    IPC: H04L12/931 ,  G06F17/50

    CPC classification number: G06F17/5063 ,  G06F2217/78 ,  H03M1/12 ,  H03M1/66

    Abstract: Described is an apparatus which comprises: logic to convert output of at least one sensor to a digital sensing signal; a router coupled to the sensor, the router to receive the digital sensing signal and to map into circuit data; and one or more communication interfaces, coupled to the router, to forward circuit data to a circuit endpoint. Described is a method which comprises: providing one or more digital sensing signals from a plurality of sensors; receiving the one or more digital sensing signals; generating packets of data using the one or more digital sensing signals; and providing the packets of data to one or more destinations.

    Abstract translation: 描述了一种装置，其包括：将至少一个传感器的输出转换为数字感测信号的逻辑; 路由器耦合到传感器，路由器接收数字感测信号并映射到电路数据中; 以及耦合到路由器的一个或多个通信接口，以将电路数据转发到电路端点。 描述了一种方法，其包括：从多个传感器提供一个或多个数字感测信号; 接收一个或多个数字感测信号; 使用所述一个或多个数字感测信号产生数据包; 并将数据包提供给一个或多个目的地。

    Apparatus and method for reducing leakage power of a circuit
    17.
    发明授权
    Apparatus and method for reducing leakage power of a circuit 有权
    减少电路漏电功率的装置和方法

    公开(公告)号：US09207750B2

    公开(公告)日：2015-12-08

    申请号：US13715624

    申请日：2012-12-14

    Applicant: Intel Corporation

    Inventor： Gururaj K. Shamanna ,  Stefan Rusu ,  Phani Kumar Kandula ,  Sankalan Prasad ,  Mandar R. Ranade ,  Narayanan Natarajan ,  Tessil Thomas

    IPC: G06F1/32

    CPC classification number: G06F1/28 ,  G05F1/625 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/14 ,  Y02D10/172

    Abstract: Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.

    Abstract translation: 描述了一种处理器，包括：多个晶体管，其可操作以提供动态可调节的晶体管尺寸，所述多个晶体管的一端耦合到第一电源并在另一端耦合到第二电源; 耦合到所述第二电源的电路，所述第二电源向所述电路提供电力; 以及功率控制单元（PCU），用于监测第一电源的电平，并且动态地调整多个晶体管的晶体管尺寸，使得调节第二电源以保持电路的可操作性。

    INTEGRATED CLOCK DIFFERENTIAL BUFFERING
    18.
    发明申请
    INTEGRATED CLOCK DIFFERENTIAL BUFFERING 有权
    集成时钟差分缓冲

    公开(公告)号：US20150188548A1

    公开(公告)日：2015-07-02

    申请号：US14513024

    申请日：2014-10-13

    Applicant: Intel Corporation

    Inventor： Choupin Huang ,  Huang K. Boddu ,  Stefan Rusu ,  Nicholas B. Peterson

    IPC: H03L7/07

    CPC classification number: H03L7/07 ,  G06F1/06 ,  G06F1/10 ,  G06F3/167 ,  H03L7/08 ,  H03L7/0891 ,  H03L2207/06

    Abstract: Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal. The first PLL circuit, the second PLL circuit, the first set of output buffers and the second set of output buffers reside within an integrated circuit package also having a die to receive at least the first differential reference clock signal.

    Abstract translation: 集成时钟差分缓冲。 具有第一时钟比率的第一锁相环（PLL）电路被耦合以接收输入差分时钟信号。 第一PLL电路产生第一参考时钟信号。 具有第二时钟比的第二PLL电路被耦合以接收输入差分时钟信号。 第二个PLL电路产生第二个参考时钟信号。 耦合第一组时钟信号输出缓冲器以接收第一参考时钟信号并提供对应于第一参考时钟信号的第一差分参考时钟信号。 第二组时钟信号输出缓冲器被耦合以接收第二参考时钟信号并提供对应于第二参考时钟信号的第二差分参考时钟信号。 第一PLL电路，第二PLL电路，第一组输出缓冲器和第二组输出缓冲器驻留在还具有至少接收第一差分参考时钟信号的管芯的集成电路封装中。

Patent Agency Ranking