公开(公告)号：US10699465B1

公开(公告)日：2020-06-30

申请号：US16235893

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Carsten Benthin ,  Karthik Vaidyanathan ,  Philip Laws ,  Scott Janus ,  Sven Woop

IPC: G06T15/00 ,  G06T15/06

Abstract: Cluster of acceleration engines to accelerate intersections. For example, one embodiment of an apparatus comprises: a set of graphics cores to execute a first set of instructions of a primary graphics thread; a scalar cluster comprising a plurality of scalar execution engines; and a communication fabric interconnecting the set of graphics cores and the scalar cluster; the set of graphics cores to offload execution of a second set of instructions associated with ray traversal and/or intersection operations to the scalar cluster; the scalar cluster comprising a plurality of local memories, each local memory associated with one of the scalar execution engines, wherein each local memory is to store a portion of a hierarchical acceleration data structure required by an associated scalar execution engine to execute one or more of the second set of instructions; the plurality of scalar execution engines to store results of the execution of the second set of instructions in a memory accessible by the set of graphics cores; wherein the set of graphics cores are to process the results within the primary graphics thread.