Acceleration Resource Scheduling Method and Apparatus, and Acceleration System

    公开(公告)号:US20200274755A1

    公开(公告)日:2020-08-27

    申请号:US15930780

    申请日:2020-05-13

    Abstract: An acceleration resource scheduling method includes: receiving an acceleration instruction sent by the virtual machine, where the acceleration instruction includes to-be-accelerated data; determining a virtual accelerator allocated to the virtual machine; determining, based on the virtual accelerator, a network accelerator that is to process the acceleration instruction, and sending the acceleration instruction to the network accelerator, so that the network accelerator sends the acceleration instruction to a physical accelerator that is to process the acceleration instruction; receiving a computing result that is returned after the physical accelerator performs acceleration computing on the to-be-accelerated data by using the physical acceleration resource; and sending the computing result to the virtual machine.

    Power Consumption Management Method and Related Device

    公开(公告)号:US20230214002A1

    公开(公告)日:2023-07-06

    申请号:US18181688

    申请日:2023-03-10

    CPC classification number: G06F1/3293 G06F9/4875 G06F9/4893

    Abstract: A power consumption management method and a related device are provided. The method may be used to manage power consumption of a device including a plurality of voltage domains, where each of the voltage domains includes at least one processor core. The method includes: during power consumption management, identifying a first voltage domain that meets a preset condition in a plurality of voltage domains, migrating tasks to be executed by all processor cores in the first voltage domain to a second voltage domain, and then setting each of working modes of components in the first voltage domain as a first mode.

    Data write method and solid-state drive array

    公开(公告)号:US11243701B2

    公开(公告)日:2022-02-08

    申请号:US16914375

    申请日:2020-06-28

    Abstract: The present invention provides a data write method and a solid-state drive array. The solid-state drive array is based on a RAID system and includes n solid-state drives. Before to-be-written data is written into the solid-state drive array, the to-be-written data is divided into n data blocks that are in a one-to-one correspondence with the n solid-state drives. After the n data blocks are all stored into the corresponding solid-state drives, FTL update of the n data blocks is performed, to complete write of the to-be-written data. If the solid-state drive array is powered off during storage of the n data blocks, because FTL update of the data blocks is not performed, all the n data blocks fail to be written into the solid-state drive array, thereby ensuring atomicity of write operations of the n data blocks.

    Failover method, apparatus and system

    公开(公告)号:US10095592B2

    公开(公告)日:2018-10-09

    申请号:US15175818

    申请日:2016-06-07

    Abstract: A failover method, apparatus and system to implement fast failover between a primary processor and a secondary processor, where the method includes receiving, by a second device, a transaction processing packet, where the transaction processing packet includes processing information about access of a host to a peripheral component interconnect express (PCIe) device, the processing information is used to describe information required for resuming a transaction when the transaction is interrupted, the second device further stores topology information of the PCIe device, and a driver for the PCIe device is loaded to the second device, and when detecting that the first device fails, continuing to process, by the second device according to the topology information, the driver, and the processing information, the transaction that is about the access of the host to the PCIe device and is being processed when a first device fails.

    Transmission Rate Determining Method and Communication Apparatus

    公开(公告)号:US20240171357A1

    公开(公告)日:2024-05-23

    申请号:US18424112

    申请日:2024-01-26

    Inventor: Junjie Wang

    CPC classification number: H04L5/0055 H04L5/0048

    Abstract: In a transmission rate determining method, a proximity coupling device (PCD) sends an activation frame to a proximity integrated circuit card (PICC). The activation frame indicates at least a first transmission rate used to transmit a first information frame and a second transmission rate used to transmit a target frame. The first information frame is used to transmit application information. The target frame includes at least one of a second information frame or a third information frame, the second information frame is used to transmit receive ready information, and the third information frame is used to transmit control information. The PCD receives an acknowledgment frame from the PICC. The acknowledgment frame indicates that the PICC has received the activation frame. Then, the PCD transmits the first information frame with the PICC at the first transmission rate, and transmits the target frame with the PICC at the second transmission rate.

    Data forwarding chip and server
    18.
    发明授权

    公开(公告)号:US11829309B2

    公开(公告)日:2023-11-28

    申请号:US17698059

    申请日:2022-03-18

    CPC classification number: G06F13/1684 G06F13/42

    Abstract: A data forwarding chip and a server are disclosed. The server includes a data forwarding chip, a network interface card, and a processor. The data forwarding chip is separately connected to the network interface card and the processor through a bus. After receiving a data forwarding request sent by the processor or the network interface card, the data forwarding chip forwards, based on a destination address of the data forwarding request through an endpoint port that is on the forwarding chip and that is directly connected to a memory space corresponding to the destination address of the data forwarding request, to-be-forwarded data specified in the data forwarding request, such that when the server sends or receives data, cross-chip transmission of data between processors occurs, thereby reducing a data transmission delay.

    REQUEST PROCESSING METHOD, SYSTEM ON CHIP, AND PUBLIC CLOUD MANAGEMENT COMPONENT

    公开(公告)号:US20210263748A1

    公开(公告)日:2021-08-26

    申请号:US17318075

    申请日:2021-05-12

    Abstract: A bare-metal server of a cloud storage management system comprises a system-on-chip (Soc) and a processor. The SoC receives a volume attaching request sent by a public cloud management component of the management system. The volume attaching request includes an identifier of a system volume storing a file for starting an operating system of a bare-metal server of the management system. The SoC stores the identifier of the system volume based on the volume attaching request. When the bare-metal server of the management system is started, the bare-metal server uses the identifier of the system volume to the system volume, and starts an operating system by means of the SoC accessing the system volume.

    DATA WRITE METHOD AND SOLID-STATE DRIVE ARRAY

    公开(公告)号:US20200326855A1

    公开(公告)日:2020-10-15

    申请号:US16914375

    申请日:2020-06-28

    Abstract: The present invention provides a data write method and a solid-state drive array. The solid-state drive array is based on a RAID system and includes n solid-state drives. Before to-be-written data is written into the solid-state drive array, the to-be-written data is divided into n data blocks that are in a one-to-one correspondence with the n solid-state drives. After the n data blocks are all stored into the corresponding solid-state drives, FTL update of the n data blocks is performed, to complete write of the to-be-written data. If the solid-state drive array is powered off during storage of the n data blocks, because FTL update of the data blocks is not performed, all the n data blocks fail to be written into the solid-state drive array, thereby ensuring atomicity of write operations of the n data blocks.

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