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公开(公告)号：US20220108655A1
公开(公告)日：2022-04-07
申请号：US17260746
申请日：2020-03-31
Inventor： Ziyang Yu , Zhu Wang , Sheng Hu , Tianliang Liu , Guo Liu
IPC: G09G3/3233
Abstract: A pixel circuit includes: pixel units, wherein each pixel unit includes a light-emitting element and a pixel driving circuit, the pixel driving circuit and the light-emitting element are electrically connected to a first node; a first compensation sub-circuit electrically connected to each pixel driving circuit, and configured to provide an initialization signal to the pixel driving circuit, obtain a voltage at the first node when the light-emitting element emits light via the pixel driving circuit, and generate a compensation data signal based on the voltage at the first node; and a second compensation sub-circuit electrically connected to each pixel driving circuit and configured to keep the voltage at the first node within a set operating voltage range of the light-emitting element. The pixel driving circuit is further configured to initialize the first node based on the initialization signal, and use the compensation data signal to drive the light-emitting element.
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公开(公告)号：US20250133936A1
公开(公告)日：2025-04-24
申请号：US18683690
申请日：2023-02-28
Inventor： Quanyong Gu , Tiaomei Zhang , Ziyang Yu , Wenbo Chen , Pan Zhao , Mengqi Wang , Erjin Zhao , Xiangnan Pan , Qingqing Yan , Qing He , Zhiliang Jiang
IPC: H10K59/80 , H10K59/131
Abstract: A displaying base board includes an active area and a peripheral region, the peripheral region includes at least a first blocking part and a second blocking part; the peripheral region further includes a first power-supply signal line, and an orthographic projection of the first power-supply signal line on a substrate of the displaying base board has an overlapping part with individually an orthographic projection of the first blocking part on the substrate and an orthographic projection of the second blocking part on the substrate; and the first power-supply signal line is provided with a plurality of openings, and a region enclosed by orthographic projections on the substrate of outer contours of some of the openings falls within a region of the orthographic projection on the substrate of at least one of the first blocking part and the second blocking part.
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公开(公告)号：US12272303B2
公开(公告)日：2025-04-08
申请号：US18294003
申请日：2023-05-23
Inventor： Ziyang Yu , Haijun Qiu , Ming Hu , Zhiliang Jiang , Tianyi Cheng , Jianpeng Wu , Mengqi Wang , Qi Wei , Wenbo Chen , Tiaomei Zhang , Sifei Ai , Cong Liu , Qian Xu
IPC: G09G3/3225
Abstract: The present disclosure provides a driving circuitry, a driving method, a driving module, and a display device. The driving circuitry includes a driving signal generation circuitry, a gating circuitry, an output control circuitry and an output circuitry. The driving signal generation circuitry is configured to perform a shifting operation on an (N−1)th-level driving signal to obtain an Nth-level driving signal. The gating circuitry is configured to write a gating input signal into a first node under the control of a gating control signal. The output control circuitry is configured to perform an NAND operation on the Nth-level driving signal and a potential at a second end of the output control circuitry to obtain a first output signal. The output circuitry is configured to perform phase inversion on the first output signal to obtain and provide an output driving signal through an output driving end, where N is a positive integer.
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公开(公告)号：US20250104643A1
公开(公告)日：2025-03-27
申请号：US18290909
申请日：2023-04-26
Inventor： Tiaomei Zhang , Mengqi Wang , Wenhui Gao , Ziyang Yu , Tianyi Cheng , Wenbo Chen , Zhiliang Jiang , Ming Hu
IPC: G09G3/3266
Abstract: This disclosure provides a display substrate, a display, and a display substrate driving method. The display substrate includes a first-category pixel row, a second-category pixel row, a first drive line, a second drive line and at least one category of data signal source; a first gate on array (GOA) circuit is used for providing a starting signal of a first frequency to the first-category pixel row; a second GOA circuit is used for providing a starting signal of a second frequency to the second-category pixel row; the at least one category of data signal source is used for supplying a data signal to data signal lines of the first-category pixel row and the second-category pixel row.
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公开(公告)号：US20250104640A1
公开(公告)日：2025-03-27
申请号：US18558393
申请日：2022-12-19
Inventor： Ziyang Yu , Haijun Qiu , Ming Hu , Zhiliang Jiang , Tianyi Cheng , Jianpeng Wu , Wenbo Chen , Mengqi Wang , Cong Liu , Qian Xu , Erjin Zhao
IPC: G09G3/3258
Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit, a voltage control circuit and a second node control circuit; the driving signal generation circuit generates an Nth stage of driving signal; the output control circuit controls to connect the first control node and the second node under the control of the potential of the first node; the gating circuit writes a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to the potential of the first node; the second node control circuit controls to connect the second node and the first voltage terminal under the control of the potential of the first node.
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Patent Agency Ranking
公开(公告)号：US20250087166A1
公开(公告)日：2025-03-13
申请号：US18558383
申请日：2022-12-19
Inventor： Ziyang Yu , Haijun Qiu , Ming Hu , Zhiliang Jiang , Tianyi Cheng , Jianpeng Wu , Wenbo Chen , Mengqi Wang , Cong Liu , Qian Xu , Qingqing Yan , Pan Zhao , Qing He , Xiangnan Pan , Quanyong Gu
IPC: G09G3/3266 , G09G3/3258
Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit and an output circuit; the driving signal generation circuit generates and outputs the Nth stage of driving signal; the gating circuit controls to write the gating input signal into the first node; the output control circuit performs a NAND operation on the Nth stage of driving signal and the potential of the second terminal of the output control circuit to obtain a first output signal; the output circuit inverts the first output signal to obtain and provide an output driving signal through the output driving terminal; N is a positive integer.
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公开(公告)号：US12236865B2
公开(公告)日：2025-02-25
申请号：US17775964
申请日：2021-06-17
Inventor： Guo Liu , Ziyang Yu , Maoying Liao
IPC: G09G3/3233 , G09G3/3291
Abstract: A method of driving a display device, where the display device includes a display substrate including a plurality of rows of pixel circuits, and in each pixel circuit, a reset compensation circuit and a data writing circuit are connected at a second node, and the reset compensation circuit is connected to a reset control signal line and a first voltage input terminal; in a driving stage, driving a light emitting device OLED connected to each of other rows of pixel circuits except a last row of pixel circuits further includes a charge maintenance stage performed after a light emission voltage generation stage; and in the stable display stage, all light emitting devices OLED simultaneously emit light; where in the charge maintenance stage, the first voltage input terminal is disconnected from the second node by the reset compensation circuit in response to control of a reset control signal.
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公开(公告)号：US20240268165A1
公开(公告)日：2024-08-08
申请号：US18041074
申请日：2022-04-29
Inventor： Ziyang Yu , Mengqi Wang , Wenbo Chen , Zhiliang Jiang
IPC: H10K59/131 , G09G3/3233
CPC classification number: H10K59/131 , G09G3/3233 , G09G2300/0426 , G09G2300/0819 , G09G2300/0842
Abstract: An array substrate is provided. The array substrate includes a plurality of light emitting elements and a plurality of pixel driving circuits configured to drive light emission in the plurality of light emitting elements. In a first region, transistors of multiple pixel driving circuits of the plurality of pixel driving circuits are present, and the plurality of light emitting elements are absent. In a second region, multiple light emitting elements of the plurality of light emitting elements are present, and transistors of the plurality of pixel driving circuits are absent.
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公开(公告)号：US20230269981A1
公开(公告)日：2023-08-24
申请号：US18184673
申请日：2023-03-16
IPC: H10K59/131 , G09G3/3233 , H10K59/124
CPC classification number: H10K59/131 , G09G3/3233 , H10K59/124 , G09G2300/0426 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2330/028
Abstract: A display panel includes a respective pixel driving circuit having a driving transistor, a first reset transistor, and a second reset transistor. First electrodes of adjacent first reset transistors respectively in adjacent pixel driving circuits along a first direction are connected by a first connecting line. First electrodes of adjacent second reset transistors respectively in the adjacent pixel driving circuits along the first direction are connected to each other by a second connecting line. The first connecting line and the second connecting line are in a semiconductor material layer. First electrodes of six adjacent first reset transistors respectively in six adjacent pixel driving circuits along the first direction are connected to three adjacent first node reset signal lines through three first vias. The first connecting line and the second connecting line extend along the first direction. The three adjacent first node reset signal lines extend along a second direction.
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公开(公告)号：US20250095590A1
公开(公告)日：2025-03-20
申请号：US18579984
申请日：2022-12-20
Inventor： Wenbo Chen , Ziyang Yu , Mengqi Wang , Tiaomei Zhang , Erjin Zhao , Quanyong Gu , Tianyi Cheng , Jianpeng Wu , Zhiliang Jiang , Ming Hu
IPC: G09G3/3266 , G11C19/28
Abstract: A shift register includes a shift module configured for causing the cascade signal output end to output a cascade signal in response to a signal of the input signal end; an reverse output module configured for causing the reverse signal output end to output a signal reverse to the cascade signal output end in response to a signal of the cascade signal output end; a latch module configured for causing an output end of the latch module to output a control signal of the masking signal end in response to signals of the cascade signal output end and the reverse signal output end of a previous level; and a selection output module configured for providing a signal of the first power supply end or the second power supply end to the driving signal output end in response to a signal of the output end of the latch module.
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