公开(公告)号：US11263138B2

公开(公告)日：2022-03-01

申请号：US16176686

申请日：2018-10-31

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Miles Robert Dooley ,  Michael Filippo

IPC: G06F12/0862

Abstract: An apparatus is provided that includes cache circuitry that comprises a plurality of cache lines. The cache circuitry treats one or more of the cache lines as trace lines each having correlated addresses and each being tagged by a trigger address. Prefetch circuitry causes data at the correlated addresses stored in the trace lines to be prefetched.

公开(公告)号：US09864694B2

公开(公告)日：2018-01-09

申请号：US14702972

申请日：2015-05-04

Applicant: ARM LIMITED

Inventor： Miles Robert Dooley ,  Todd Rafacz ,  Guy Larri

IPC: G06F12/00 ,  G06F12/0895 ,  G06F12/0864 ,  G06F12/1027

CPC classification number: G06F12/0895 ,  G06F12/0864 ,  G06F12/1027 ,  Y02B70/30 ,  Y02D10/13

Abstract: A cache is provided comprising a plurality of ways, each way of the plurality of ways comprising a data array, wherein a data item stored by the cache is stored in the data array of one of the plurality of ways. A way tracker of the cache has a plurality of entries, each entry of the plurality of entries for storing a data item identifier and for storing, in association with the data item identifier, an indication of a selected way of the plurality of ways to indicate that a data item identified by the data item identifier is stored in the selected way. Each entry of the way tracker is further for storing a miss indicator in association with the data item identifier, wherein the miss indicator is set by the cache when a lookup for a data item identified by that data item identifier has resulted in a cache miss. A corresponding method of caching data is also provided.