公开(公告)号：US10859628B2

公开(公告)日：2020-12-08

申请号：US16375344

申请日：2019-04-04

Applicant: Apple Inc.

Inventor： Bibo Li ,  Bo Yang ,  Vijay M. Bettada ,  Matthias Knoth ,  Toshinari Takayanagi

IPC: G01R31/317 ,  G01R19/00 ,  H03M1/12 ,  G01R31/3177

Abstract: An apparatus includes a functional circuit, including a power supply node, and a test circuit. The functional circuit is configured to operate in a test mode that includes generating respective test output patterns in response to application of a plurality of test stimulus patterns. The test circuit is configured to identify a particular test stimulus pattern of the plurality of test stimulus patterns, and to reapply the particular test stimulus pattern to the functional circuit multiple times. The test circuit is further configured to vary, for each reapplication, a start time of the particular test stimulus pattern in relation to when a voltage level of the power supply node is sampled for that reapplication.

公开(公告)号：US09658634B2

公开(公告)日：2017-05-23

申请号：US14673326

申请日：2015-03-30

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Eric G. Smith ,  Erik P. Machnicki ,  Jung Wook Cho ,  Khaled M. Alashmouny ,  Kiran B. Kattel ,  Vijay M. Bettada ,  Bo Yang ,  Wenlong Wei

IPC: G06F1/00 ,  G05F3/02 ,  G06F1/32

CPC classification number: G05F3/02 ,  G06F1/324 ,  G06F1/3296

Abstract: An under voltage detection circuit and method of operating an IC including the same is disclosed. In one embodiment, an IC includes an under voltage protection circuit having first and second comparators configured to compare a supply voltage to first and second voltage thresholds, respectively, with the second voltage threshold being greater than the first. A logic circuit is coupled to receive signals from the first and second comparators. During operation in a high performance state by a corresponding functional circuit, the logic circuit is configured to cause assertion of a throttling signal responsive to an indication that the supply voltage has fallen below the first threshold. A clock signal provided to the functional circuit may be throttled responsive to the indication. If the supply voltage subsequently rises to a level above the second threshold, the throttling signal may be de-asserted.

公开(公告)号：US20140088912A1

公开(公告)日：2014-03-27

申请号：US13624372

申请日：2012-09-21

Applicant: APPLE INC.

Inventor： Anuja Banerjee ,  Samy R. Makar ,  Vijay M. Bettada

IPC: G01R31/26 ,  G06F19/00

CPC classification number: G01R31/318594

Abstract: A method and apparatus for conducting a transition test of a source synchronous interface is disclosed. A system includes a source synchronous transmitter and source synchronous receiver. The source synchronous transmitter includes a first scannable flop having an output coupled to a data input of a second scannable flop in the source synchronous receiver. During a transition test, the source synchronous transmitter is configured to transmit data from the first scannable flop to the second scannable flop, along with a clock signal at an operational clock speed. The first scannable flop is coupled to feedback circuitry configured to cause transitions of the transmitted data. The second scannable flop may capture the transmitted data. The captured data may be subsequently used to determine if the desired transitions were detected by the second scannable flop.

Abstract translation: 公开了一种用于进行源同步接口的转换测试的方法和装置。 系统包括源同步发射机和源同步接收机。 源同步发射机包括第一可扫描触发器，其具有耦合到源同步接收器中的第二可扫描触发器的数据输入的输出。 在转换测试期间，源同步发射机被配置为将数据从第一可扫描触发器发送到第二可扫描触发器，以及以操作时钟速度的时钟信号。 第一可扫描触发器耦合到被配置为引起发送数据的转换的反馈电路。 第二个可扫描的触发器可以捕获所发送的数据。 捕获的数据可以随后用于确定是否由第二可扫描的翻转器检测到期望的转换。