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公开(公告)号：US10146732B2
公开(公告)日：2018-12-04
申请号：US13747205
申请日：2013-01-22
Applicant: Apple Inc.
Inventor： Girault W. Jones , Nathan A. Johanningsmeier , Casey L. Hardy
Abstract: An audio system bus has a bus data line and a bus clock line. Audio producers are coupled to the bus to form a time-division multiplexed multi drop bus interface arrangement having protocol slots 0, 1, . . . N where N is an integer greater than two. A bus device is coupled to the bus that produces a) a frame marker on the bus data line in slot 0, and b) a data bit on the bus data line in slot 1. The audio producers are to produce their respective audio data bits in their assigned slots other than slots 0 and 1. Other embodiments are also described and claimed.
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公开(公告)号：US09729964B2
公开(公告)日：2017-08-08
申请号：US14315863
申请日：2014-06-26
Applicant: Apple Inc.
Inventor： Roderick B. Hogan , Girault W. Jones , Nathan A. Johanningsmeier
IPC: H04R3/00
CPC classification number: H04R3/00 , H04R2420/09 , H04R2499/13
Abstract: A method for audio signal processing, where an audio amplifier drives a load through a connector, using 1) an input audio signal, and 2) a signal from a return pin of the connector. Output headroom of the audio amplifier is automatically detected, while the amplifier is driving the load. A variable resistor circuit that is coupled to provide variable resistance between the return pin of the connector and a ground plane, is automatically adjusted, in response to the detected output headroom of the amplifier. Other embodiments are also described and claimed.
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公开(公告)号：US11025406B2
公开(公告)日：2021-06-01
申请号：US16584012
申请日：2019-09-26
Applicant: Apple Inc.
Inventor： Michael F. Jean , Adam E. Kriegel , Brett D. George , Daniel C. Klingler , Girault W. Jones , Felipe Ferreri Tonello
Abstract: A system and method to mitigate the temporary loss of the input sampling clocks when receiving audio data over the ARC or eARC interface of HDMI are provided. A media device may substitute an externally generated clock derived from a local crystal oscillator of the media device for the missing input sampling clock. The external clock may be synchronized to the frequency of the input sampling clock. The media device may synchronize the external clock to the audio data when there is a loss of the input sampling clock. When the input sampling clock of the audio data reappears, the media device may switch back from the external clock to the input sampling clock. When transitioning between the input sampling clock and the external clock, the media device may insert zero padding into the audio data samples to mute any potential glitch in the sound from an audio playback device.
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公开(公告)号：US10825480B2
公开(公告)日：2020-11-03
申请号：US15610431
申请日：2017-05-31
Applicant: Apple Inc.
Inventor： Todd P. Marco , Girault W. Jones , Kavitha Srinivasan , Aram M. Lindahl
Abstract: A method for automatically producing a video and audio mix at a first portable electronic device. The method receives a request to capture video and audio, performs a network discovery process to find a second portable electronic device, and sends a message to the second device indicating when to start recording audio for a double system recording session. The method initiates the recording session, such that both devices record concurrently. In response to the first device stopping the recording of audio and sound, signaling the second device to stop recording for the identified recording session. In response to the first device receiving a first audio track from the second device that contains an audio signal recorded during the recording session, automatically generating a mix of video and audio, such that one of the audio signals from the first and second tracks is ducked relative to the other.
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Patent Agency Ranking
公开(公告)号：US10212500B2
公开(公告)日：2019-02-19
申请号：US15418395
申请日：2017-01-27
Applicant: Apple Inc.
Inventor： Roderick B. Hogan , Girault W. Jones , Nathan A. Johanningsmeier
Abstract: An analog to digital conversion circuit receives a transducer output signal and outputs a data bitstream, where a latch or flip flop has an input that receives a clock signal. An AC-DC power converter receives the clock signal and produces a DC voltage which may power the analog to digital conversion circuit. The AC-DC power converter has a rectifier, an energy store and a voltage regulator, charge pump or filter, which draws power from the energy store to produce the DC voltage. A control circuit delays replenishment of the energy store by the rectified clock signal, responsive to the clock signal. Other embodiments are also described and claimed.
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公开(公告)号：US20180220214A1
公开(公告)日：2018-08-02
申请号：US15418395
申请日：2017-01-27
Applicant: Apple Inc.
Inventor： Roderick B. Hogan , Girault W. Jones , Nathan A. Johanningsmeier
Abstract: An analog to digital conversion circuit receives a transducer output signal and outputs a data bitstream, where a latch or flip flop has an input that receives a clock signal. An AC-DC power converter receives the clock signal and produces a DC voltage which may power the analog to digital conversion circuit. The AC-DC power converter has a rectifier, an energy store and a voltage regulator, charge pump or filter, which draws power from the energy store to produce the DC voltage. A control circuit delays replenishment of the energy store by the rectified clock signal, responsive to the clock signal. Other embodiments are also described and claimed.
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公开(公告)号：US09653079B2
公开(公告)日：2017-05-16
申请号：US14621093
申请日：2015-02-12
Applicant: Apple Inc.
Inventor： Manu Gulati , Gilbert H. Herbeck , Alexei E. Kosut , Girault W. Jones , Timothy J. Millet
CPC classification number: G10L15/28 , G10L15/08 , G10L15/22 , G10L2015/088 , G10L2015/223
Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.
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公开(公告)号：US20160240193A1
公开(公告)日：2016-08-18
申请号：US14621093
申请日：2015-02-12
Applicant: Apple Inc.
Inventor： Manu Gulati , Gilbert H. Herbeck , Alexei E. Kosut , Girault W. Jones , Timothy J. Millet
CPC classification number: G10L15/28 , G10L15/08 , G10L15/22 , G10L2015/088 , G10L2015/223
Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.
Abstract translation: 在一个实施例中，芯片上的系统（SOC）可以包括一个或多个中央处理单元（CPU），存储器控制器和被配置为当SOC的其余部分断电时保持通电的电路。 该电路可以被配置为接收音频采样并将这些音频样本与预定模式相匹配。 在SOC的其余部分断电的时间内，电路可以根据第一时钟进行操作。 响应于检测样本中的预定模式，电路可以使存储器控制器和处理器加电。 在上电过程中，具有比第一时钟具有一个或多个更好特征的第二时钟可以变得可用。 电路可以切换到第二时钟，同时保持采样，或者丢失至多一个采样，或者不超过阈值数量的采样。
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公开(公告)号：US20140113492A1
公开(公告)日：2014-04-24
申请号：US13913255
申请日：2013-06-07
Applicant: Apple Inc.
Inventor： Joshua Funamura , Nathan Johanningsmeier , Niel D. Warren , Girault W. Jones
IPC: H01R13/66
Abstract: Audio jack optical modules that may have a reduced size. Various examples may provide an optical module for an audio jack where a driver circuit is omitted from the optical module and instead placed either elsewhere in the audio jack or separately outside the audio jack. In some examples, the driver may be integrated with a logic circuit, such as a coder-decoder (CODEC) or other logic circuit. Other examples may provide an optical module for an audio jack where a lens for a light-emitting diode is omitted. In some examples, a higher-power light-emitting diode may be used. These light-emitting diodes may be strong enough to provide a requisite amount of light to a detector in, or associated with, an audio plug.
Abstract translation: 可能具有减小尺寸的音频插孔光学模块。 各种示例可以提供用于音频插孔的光学模块，其中从光学模块省略驱动器电路，而是将其放置在音频插孔的其他地方或单独地在音频插孔外部。 在一些示例中，驱动器可以与诸如编码器 - 解码器（CODEC）或其他逻辑电路的逻辑电路集成。 其他示例可以提供用于音频插孔的光学模块，其中省略了用于发光二极管的透镜。 在一些示例中，可以使用更高功率的发光二极管。 这些发光二极管可能足够强以向音频插头中的或与其相关联的检测器提供必需量的光。
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