公开(公告)号：US08620436B2

公开(公告)日：2013-12-31

申请号：US11550763

申请日：2006-10-18

申请人： Jordi Parramon ,  David K. L. Peterson ,  Paul J. Griffith

发明人： Jordi Parramon ,  David K. L. Peterson ,  Paul J. Griffith

IPC分类号： A61N1/02

CPC分类号： A61N1/36125 ,  A61N1/0531 ,  A61N1/0534 ,  A61N1/0541 ,  A61N1/0543 ,  A61N1/0551 ,  A61N1/36071

摘要： Disclosed herein is a current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG). Current source and sink circuitry are both divided into coarse and fine portions, which respectively can provide a coarse and fine current resolution to a specified electrode on the IPG. The coarse portion is distributed across all of the electrodes and so can source or sink current to any of the electrodes. The coarse portion is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking a coarse amount of current to or from any one of the electrodes on the device. The fine portion of the current generation circuit preferably includes source and sink circuitry dedicated to each of the electrode on the device, which can comprise digital-to-analog current converters (DACs). The DACs also receives the above-noted reference current, which is amplified by the DACs in fine increments by appropriate selection of fine current control signals. When the coarse and fine current control circuitry are used in tandem, ample current with a fine current resolution can be achieved at any electrode and in a space- and power-efficient manner.

摘要翻译： 本文公开了用于植入式脉冲发生器（IPG）的植入式刺激器装置的当前一代架构。 电流源和接收电路都分为粗细部分，分别可以为IPG上的指定电极提供粗细和精细的电流分辨率。 粗糙部分分布在所有电极上，因此可以将电流吸收或吸收到任何电极。 粗略部分被分成多个级，每个级能够经由相关联的开关组，该器件对设备上的任何一个电极进行粗电流的吸收或吸收。 电流产生电路的优良部分优选地包括专用于器件上每个电极的源极和漏极电路，其可以包括数模转换器（DAC）。 DAC还接收上述参考电流，其通过适当选择精细电流控制信号以细微增量由DAC放大。 当粗调和精细电流控制电路串联使用时，可以在任何电极上以空间和功率有效的方式实现具有精细电流分辨率的充足电流。

公开(公告)号：US20110015705A1

公开(公告)日：2011-01-20

申请号：US12883797

申请日：2010-09-16

申请人： Paul J. Griffith ,  Jordi Parramon ,  Goran N. Marnfeldt ,  Daniel Aghassisn ,  Kiran Nimmagadda ,  Emanuel Feldman ,  Jess W. Shi

发明人： Paul J. Griffith ,  Jordi Parramon ,  Goran N. Marnfeldt ,  Daniel Aghassisn ,  Kiran Nimmagadda ,  Emanuel Feldman ,  Jess W. Shi

IPC分类号： A61N1/08

CPC分类号： A61N1/36125 ,  A61N1/025 ,  A61N1/0551 ,  A61N1/0553 ,  A61N1/36071

摘要： An improved architecture for an implantable medical device such as an implantable pulse generator (IPG) is disclosed. In one embodiment, the various functional blocks for the IPG are incorporated into a signal integrated circuit (IC). Each of the functional blocks communicate with each other, and with other off-chip devices if necessary, via a centralized bus governed by a communication protocol. To communicate with the bus and to adhere to the protocol, each circuit block includes bus interface circuitry adherent with that protocol. Because each block complies with the protocol, any given block can easily be modified or upgraded without affecting the design of the other blocks, facilitating debugging and upgrading of the IPG circuitry. Moreover, because the centralized bus can be taken off the integrated circuit, extra circuitry can easily be added off chip to modify or add functionality to the IPG without the need for a major redesign of the main IPG IC.

摘要翻译： 公开了一种用于植入式医疗装置（例如植入式脉冲发生器（IPG））的改进的架构。 在一个实施例中，用于IPG的各种功能块被并入到信号集成电路（IC）中。 每个功能块通过由通信协议管理的集中式总线彼此通信，并且如果需要，与其他片外设备通信。 为了与总线进行通信并遵守协议，每个电路块包括与该协议相关的总线接口电路。 由于每个块符合协议，任何给定的块都可以轻松修改或升级，而不影响其他块的设计，便于IPG电路的调试和升级。 此外，由于集中式总线可以从集成电路中取出，所以额外的电路可以轻松地从芯片上添加到IPG中，以便对IPG进行主要的重新设计。

公开(公告)号：US4330723A

公开(公告)日：1982-05-18

申请号：US65991

申请日：1979-08-13

申请人： Paul J. Griffith

发明人： Paul J. Griffith

IPC分类号： H03K19/088 ,  H03K19/013 ,  H03K5/12 ,  H03K19/084

CPC分类号： H03K19/0136

摘要： A transistor logic output device is provided with an active element discharging transistor coupled between the base of the pulldown element transistor and ground or low potential for actively controlling a route to ground or low potential for diverting and discharging the so-called capacitive feedback Miller current generated during the low to high potential transition at the output of the device resulting from base-collector junction capacitance in the pulldown element transistor. The active element discharging transistor is controlled at its base by the potential at the collector of the phase splitter element and is coupled to follow changes in voltage at the phase splitter collector for receiving base drive current during the transition from low to high potential at the device output and when the phase splitter is not conducting. The active element thereby provides a low impedance path to ground or low potential at the base of the pulldown element transistor means for diverting and discharging the capacitive Miller feedback current. When the phase splitter is conducting, the active element discharge transistor is deprived of base drive current and affords a high impedance.

摘要翻译： 晶体管逻辑输出装置设置有耦合在下拉元件晶体管的基极和接地或低电位之间的有源元件放电晶体管，用于主动地控制到地的线路或低电位，用于转移和放电所产生的所谓的电容反馈米勒电流 在由下拉元件晶体管中的基极 - 集电极结电容引起的器件输出端的低电位到高电位转变期间。 有源元件放电晶体管在其基极处被控制在相位分离器元件的集电极处的电位，并且被耦合以跟随在分相器集电极处的电压的变化，以在器件从低电平转换到高电位期间接收基极驱动电流 当分相器不导通时。 因此，有源元件在下拉元件晶体管装置的基极处提供到地或低电位的低阻抗路径，用于转移和放电电容米勒反馈电流。 当分相器导通时，有源元件放电晶体管被剥夺基极驱动电流并提供高阻抗。