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11.发明授权Flash memory device and program method of flash memory device using different voltages 有权闪存器件和使用不同电压的闪存器件的程序方法公开(公告)号：US07852682B2
公开(公告)日：2010-12-14
申请号：US11830260
申请日：2007-07-30
Applicant: Dae-Seok Byeon , Young-Ho Lim
Inventor： Dae-Seok Byeon , Young-Ho Lim
IPC: G11C16/06
CPC classification number: G11C16/0483 , G11C16/10
Abstract: A flash memory and a program method of the flash memory include applying a pass voltage to word lines to boost a channel voltage, which is discharged to a ground voltage. A program voltage is applied to a selected word line and a local voltage is applied to at least one word line supplied with the pass voltage while the program voltage is being applied to the selected word line. The local voltage is lower than the pass voltage and equal to or higher than the ground voltage. The boosted channel voltage may be discharged before the program voltage is applied to the selected word line.
Abstract translation: 闪速存储器和闪速存储器的编程方法包括对字线施加通过电压以升高被释放到接地电压的通道电压。 一个编程电压被施加到所选择的字线，并且当编程电压被施加到所选择的字线时，局部电压被施加到提供有通过电压的至少一个字线。 局部电压低于通过电压，等于或高于接地电压。 在将编程电压施加到所选择的字线之前，升压的通道电压可以被放电。
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公开(公告)号：US07697347B2
公开(公告)日：2010-04-13
申请号：US11972819
申请日：2008-01-11
Applicant: Dae-seok Byeon
Inventor： Dae-seok Byeon
IPC: G11C7/10
CPC classification number: G11C16/20
Abstract: A method of driving a non-volatile memory device includes supplying power to the memory device, in which setting information related to setting an operating environment is copied and stored in multiple of regions of a memory cell array. An initial read operation of the memory cell array is performed and initial setting data is determined based on the initial read operation. The operating environment of the memory device is set based on the initial setting data. Corresponding portions of the stored copies of the setting information are read at the same time.
Abstract translation: 一种驱动非易失性存储器件的方法包括向存储器件供电，其中与存储器单元阵列的多个区域复制和存储与设置操作环境有关的设置信息。 执行存储单元阵列的初始读取操作，并且基于初始读取操作来确定初始设置数据。 基于初始设定数据设定存储装置的运行环境。 同时读取设置信息的存储副本的相应部分。
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13.发明授权Flash memory devices configured to be programmed using variable initial program loops and related devices 有权配置为使用可变初始程序循环和相关设备编程的闪存设备
公开(公告)号：US07529134B2
公开(公告)日：2009-05-05
申请号：US11439797
申请日：2006-05-24
Applicant: Wook-Ghee Hahn , Young-Ho Lim , Dae-Seok Byeon
Inventor： Wook-Ghee Hahn , Young-Ho Lim , Dae-Seok Byeon
IPC: G11C16/04
CPC classification number: G11C16/30 , G11C5/145 , G11C8/08 , G11C16/04 , G11C16/08 , G11C16/12 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/1202
Abstract: A method of programming a nonvolatile memory device including a plurality of memory cells includes providing a plurality of program loops having a corresponding plurality of program voltages associated therewith. A first one of the plurality of program loops is activated to generate a first program voltage to program a first one of the plurality of memory cells. A second one of the plurality of program loops is activated to generate a second program voltage to program a second one of the plurality of memory cells.
Abstract translation: 包括多个存储器单元的非易失性存储器件的编程方法包括提供具有与其相关联的相应多个编程电压的多个程序循环。 多个程序循环中的第一个被激活以产生第一编程电压以编程多个存储器单元中的第一个。 多个程序循环中的第二个程序循环被激活以产生第二编程电压以编程多个存储器单元中的第二个。
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14.发明申请INTERNAL VOLTAGE GENERATOR AND CONTROL METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE AND SYSTEM INCLUDING THE SAME 有权内部电压发生器及其控制方法及其半导体存储器件及其系统
公开(公告)号：US20090021985A1
公开(公告)日：2009-01-22
申请号：US12175494
申请日：2008-07-18
Applicant: Dae-Seok Byeon
Inventor： Dae-Seok Byeon
CPC classification number: G11C29/02 , G11C5/147 , G11C16/30 , G11C29/021 , G11C29/028
Abstract: An internal voltage of a semiconductor memory device is controlled, where the internal voltage is set according to a reference voltage. The reference voltage is controlled according to first control data to increase the internal voltage to be higher than a target voltage in a power-up operation, and second control data is read. The reference voltage is then controlled according to the second control data to decrease the internal voltage to the target voltage.
Abstract translation: 控制半导体存储器件的内部电压，其中根据参考电压设置内部电压。 根据第一控制数据控制参考电压，以在上电操作中将内部电压增加到高于目标电压，并且读取第二控制数据。 然后根据第二控制数据控制参考电压，以将内部电压降低到目标电压。
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15.发明申请NON-VOLATILE MEMORY DEVICES AND SYSTEMS INCLUDING BAD BLOCKS ADDRESS RE-MAPPED AND METHODS OF OPERATING THE SAME 有权非易失性存储器件和系统，包括封装地址重新映射及其操作方法
公开(公告)号：US20080285347A1
公开(公告)日：2008-11-20
申请号：US12122369
申请日：2008-05-16
Applicant: Dae Seok Byeon
Inventor： Dae Seok Byeon
CPC classification number: G11C29/76
Abstract: A method of operating a non-volatile memory device included in a memory card can be provided by re-mapping addresses of bad blocks in a first non-volatile MAT in a memory card and re-mapping addresses of bad blocks in a second non-volatile MAT in the memory card, the second non-volatile MAT including blocks that are address mapped with blocks in the first non-volatile MAT. Also a method of scanning a non-volatile memory device for bad blocks can be provided by sequentially scanning blocks in a non-volatile memory device for data indicating that a respective block is a bad block starting at a starting block address that is above a lowermost block address of the non-volatile memory device, wherein the starting block address is based on a yield for the non-volatile memory device.
Abstract translation: 可以通过重新映射存储卡中的第一非易失性MAT中的坏块的地址并在第二非易失性存储卡中重新映射坏块的地址来提供操作包括在存储卡中的非易失性存储器件的方法， 存储卡中的易失性MAT，第二非易失性MAT包括在第一非易失性MAT中用块映射的地址的块。 也可以通过在非易失性存储器件中顺序地扫描块来提供用于扫描不良块的非易失性存储器件的方法，用于指示相应块是从低于最低位置的起始块地址开始的坏块 所述非易失性存储器件的块地址，其中所述起始块地址基于所述非易失性存储器件的产量。
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16.发明授权Nonvolatile semiconductor memory device having bitlines extending from cell array in single direction 有权非易失性半导体存储器件具有从单元阵列沿单向延伸的位线
公开(公告)号：US07405978B2
公开(公告)日：2008-07-29
申请号：US11513157
申请日：2006-08-31
Applicant: Wook-Ghee Hahn , Dae Seok Byeon
Inventor： Wook-Ghee Hahn , Dae Seok Byeon
IPC: G11C16/24
Abstract: A semiconductor memory device comprises a cell array including a plurality of memory cells. The semiconductor memory device further comprises a plurality of bitlines formed in a bit layer and connected to the plurality of memory cells, wherein the bitlines extend from the cell array along a single direction. A common source line is formed in a common source layer and adapted to provide a predetermined source voltage to the plurality of memory cells. A voltage control block comprising a plurality of voltage control circuits adapted to control the voltage levels of the plurality of bitlines through voltage supply lines formed in a voltage-line metal layer is formed on one side of the cell array.
Abstract translation: 半导体存储器件包括包括多个存储单元的单元阵列。 半导体存储器件还包括形成在位层中并连接到多个存储器单元的多个位线，其中位线沿着单个方向从单元阵列延伸。 公共源极线形成在公共源层中并且适于向多个存储器单元提供预定的源极电压。 电压控制块包括多个电压控制电路，其适于通过形成在电压线金属层中的电压供给线来控制多个位线的电压电平，该电压控制电路形成在电池阵列的一侧。
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17.发明申请
公开(公告)号：US20080123417A1
公开(公告)日：2008-05-29
申请号：US11605227
申请日：2006-11-29
Applicant: Dae-Seok Byeon , Young-Ho Lim
Inventor： Dae-Seok Byeon , Young-Ho Lim
Abstract: A semiconductor memory device comprises a first pump clock generator configured to generate a first pump clock signal based on a first power supply voltage. The device also comprises a first charge pump configured to generate a first pump output voltage in response to the first pump clock signal. The device also comprises a second pump clock generator configured to generate a second pump clock signal based on the first pump output voltage. The device also comprises a second charge pump configured to generate a second pump output voltage in response to the second pump clock signal. The device also comprises a third pump clock generator configured to generate a third pump clock signal based on the first power supply voltage. The device also comprises a third charge pump configured to generate a third pump output voltage in response to the third pump clock signal.
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公开(公告)号：US20060133145A1
公开(公告)日：2006-06-22
申请号：US11283646
申请日：2005-11-21
Applicant: Jin-Sung Park , Dae-Seok Byeon
Inventor： Jin-Sung Park , Dae-Seok Byeon
IPC: G11C16/04
CPC classification number: G11C16/10 , G11C2216/14
Abstract: A flash memory device is programmed by loading first data into a page buffer of a first mat. Second data is loaded into a page buffer of a second mat while programming the first data in a first memory block of the first mat.
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公开(公告)号：US20060082411A1
公开(公告)日：2006-04-20
申请号：US11167983
申请日：2005-06-27
Applicant: Jin-Sung Park , Dae-Seok Byeon
Inventor： Jin-Sung Park , Dae-Seok Byeon
IPC: G05F1/10
CPC classification number: G05F1/575
Abstract: Disclosed is a voltage regulator capable of reducing a set-up time. A driver is connected between a power supply terminal and the output terminal, and supplies a power supply voltage to the output terminal in response to a signal of a control node. A first signal generator provides a first signal to the control node when a voltage of the output terminal is lower than the target voltage. A second signal generator provides a second signal to the control node for a predetermined period of time when the voltage of the output terminal becomes higher than a detection voltage while the first signal generator is providing the first signal to the control node.
Abstract translation: 公开了一种能够减少设置时间的电压调节器。 驱动器连接在电源端子和输出端子之间，并且响应于控制节点的信号将电源电压提供给输出端子。 当输出端子的电压低于目标电压时，第一信号发生器向控制节点提供第一信号。 当第一信号发生器向控制节点提供第一信号时，第二信号发生器在输出端的电压变得高于检测电压的预定时间段内向控制节点提供第二信号。
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20.发明授权Flash memory devices that support efficient memory locking operations and methods of operating flash memory devices 有权支持高效内存锁定操作的闪存设备和操作闪存设备的方法
公开(公告)号：US06975547B2
公开(公告)日：2005-12-13
申请号：US10820245
申请日：2004-04-06
Applicant: Dae Seok Byeon , Seung-Jae Lee
Inventor： Dae Seok Byeon , Seung-Jae Lee
Abstract: Flash memory devices include at least one flash memory array and an address compare circuit that is configured to indicate whether an applied row address associated with a first operation (e.g., program, erase) is within or without an unlock area of the at least one flash memory array. A control circuit is also provided. This control circuit is configured to block performance of the first operation on the flash memory array in response to detecting an indication from the address compare circuit that the applied row address is outside the unlock area of the flash memory array.
Abstract translation: 闪存设备包括至少一个闪存阵列和地址比较电路，其被配置为指示与第一操作（例如，程序，擦除）相关联的应用行地址是否在至少一个闪存的解锁区域内 内存阵列 还提供控制电路。 响应于检测到来自地址比较电路的指示，所施加的行地址在闪存阵列的解锁区域之外，该控制电路被配置为阻止闪速存储器阵列上的第一操作的性能。
