公开(公告)号：US09728526B2

公开(公告)日：2017-08-08

申请号：US13904770

申请日：2013-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Eugene Jinglun Tam

IPC: H01L25/18 ,  G11C5/06

CPC classification number: H01L25/18 ,  G11C5/06 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used. The pads of the memory chip can be configurable to swap input and output pads to more efficiently form the memory chips into a package.

公开(公告)号：US09721629B2

公开(公告)日：2017-08-01

申请号：US15394009

申请日：2016-12-29

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Kyung Suk Oh

IPC: G11C5/06 ,  G11C7/22 ,  G11C29/02

CPC classification number: G11C7/22 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4063 ,  G11C11/4097 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028

Abstract: A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A first memory device includes a first set of one or more control registers storing a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the first memory device, and a second memory device includes a second set of one or more control registers storing a second ODT value different from the first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the second memory device.

公开(公告)号：US09711188B2

公开(公告)日：2017-07-18

申请号：US15141967

申请日：2016-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Hwang ,  Han-Soo Kim ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Sun-Il Shim ,  Jae-Hun Jeong ,  Ki-Hyun Kim

IPC: H01L27/112 ,  G11C5/06 ,  H01L27/115 ,  H01L27/11517

CPC classification number: G11C5/06 ,  H01L23/5283 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11517

Abstract: A vertical non-volatile memory device includes a substrate, and a first stack of word lines and a second stack of word lines extending in a first direction on the substrate and separated from each other in a second direction perpendicular to the first direction. The device further includes first array lines extending in the second direction on the first and the second stack, and connected to word lines of the first and the second stack through at least two of first via contacts in a same level. The device further include first word select lines being in a same level and extending in the first direction, and connected to each of the first array lines through at least one of second via contacts. Ends of each of the first and the second stack have a form of stairs on the substrate.

公开(公告)号：US20170200676A1

公开(公告)日：2017-07-13

申请号：US15383213

申请日：2016-12-19

Applicant: Da Woon JEONG ,  Sung-Hun LEE ,  Seokjung YUN ,  Hyunmog PARK ,  JoongShik SHIN ,  Young-Bae YOON

Inventor： Da Woon JEONG ,  Sung-Hun LEE ,  Seokjung YUN ,  Hyunmog PARK ,  JoongShik SHIN ,  Young-Bae YOON

IPC: H01L23/528 ,  H01L27/11556 ,  H01L27/1157 ,  G11C16/04 ,  H01L23/522 ,  H01L21/768 ,  G11C16/08 ,  H01L27/11524 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  G11C5/025 ,  G11C5/06 ,  H01L21/76816 ,  H01L21/76877 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L28/00

Abstract: Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region. Each of the intermediate stack structures exposes the third stair step structure of the intermediate stack structure disposed thereunder.

公开(公告)号：US09705005B2

公开(公告)日：2017-07-11

申请号：US14828669

申请日：2015-08-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H01L29/66 ,  H01L29/786 ,  G11C16/04 ,  G11C16/28 ,  H01L21/02 ,  H01L27/06 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/12 ,  G11C11/24 ,  H01L29/26 ,  H01L29/22 ,  G11C5/06 ,  G11C5/14 ,  G11C7/12 ,  H01L23/528 ,  H01L29/24 ,  H01L29/78 ,  H01L27/115 ,  G11C7/18 ,  G11C11/4097

CPC classification number: G11C7/10 ,  G11C5/06 ,  G11C5/147 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/08 ,  G11C11/24 ,  G11C11/4097 ,  G11C16/0433 ,  G11C16/28 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/22 ,  H01L29/24 ,  H01L29/26 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation. Furthermore, the semiconductor device is well adapted to store multivalued data. Manufacturing methods, application circuits and driving/reading methods are explained in details in the description.

公开(公告)号：US20170194039A1

公开(公告)日：2017-07-06

申请号：US15371062

申请日：2016-12-06

Applicant: Renesas Electronics Corporation

Inventor： Toshihiko FUNAKI

IPC: G11C7/10 ,  G11C5/06 ,  G11C7/22 ,  G11C5/02

CPC classification number: G11C7/10 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/22 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2218 ,  G11C2207/229

Abstract: A stack memory includes a base chip, a memory chip stacked over the base chip, and a via 42 provided between the base chip and the memory chip. The base chip has an external interface circuit and a late write control circuit. The external interface circuit externally receives/transmits write data and read data. The late write control circuit has at least a register storing write data externally supplied through the external interface circuit. The memory chip has a memory cell array and a late write control circuit having at least a register storing write data supplied from the register through the via.

公开(公告)号：US09691445B2

公开(公告)日：2017-06-27

申请号：US15306796

申请日：2015-04-30

Applicant: Bar-Ilan University

Inventor： Robert Giterman ,  Adam Teman ,  Pascal Meinerzhagen ,  Andreas Burg ,  Alexander Fish

IPC: G11C5/06 ,  G11C7/10 ,  G11C11/4097 ,  G11C11/412 ,  G11C5/02 ,  H01L27/11

CPC classification number: G11C7/10 ,  G11C5/025 ,  G11C5/06 ,  G11C11/403 ,  G11C11/4097 ,  G11C11/412 ,  H01L27/11 ,  H01L27/1104

Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The gain cell also includes a write transistor, retention element and read transistor. Each of the transistors includes a respective first diffusion connection, gate connection and second diffusion connection. The write transistor first diffusion connection is connected to the write bit line input and the write transistor gate connection is connected to the write trigger input. The read transistor first diffusion connection being connected to the read bit line output and the second diffusion connection is connected to the read trigger input. The retention element buffers between write transistor and the read transistor during data retention. The retention element also connects or disconnects a write transistor diffusion connection to/from a constant voltage in accordance with a retained data level at the read transistor gate connection.

公开(公告)号：US09691438B2

公开(公告)日：2017-06-27

申请号：US15016024

申请日：2016-02-04

Applicant: SK hynix Inc.

Inventor： Seol Hee Lee

IPC: G11C5/06 ,  G11C8/08 ,  G11C8/14

CPC classification number: G11C5/063 ,  G11C5/06 ,  G11C8/08 ,  G11C8/14

Abstract: A semiconductor device includes: first and second memory cell regions disposed adjacent to each other in a first direction, and suitable for sharing a sub-word line driving signal, and a first sub-word line driving unit disposed in a crossing area that is disposed between the first and second memory cell regions in a diagonal direction. The first sub-word line driving unit includes a first sub-word line driver for driving the first memory cell regions, a second sub-word line driver for driving the second memory cell regions, and an interconnection for transmitting the sub-word line driving signal, which extends in the first direction.

公开(公告)号：US20170178730A1

公开(公告)日：2017-06-22

申请号：US15443548

申请日：2017-02-27

Applicant: Micron Technology, Inc.

Inventor： Koji Sakui

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C5/06 ,  G11C5/144 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first transistor has a gate and is coupled between the data line and the first memory cell. The apparatus can include a second memory cell and a second select transistor having a gate. The apparatus can include a third select transistor having a gate. The second select transistor is coupled between the second memory cell and the third select transistor. The third select transistor is coupled between the second select transistor and a source. The apparatus can include a drive transistor coupled to both the gate of the first select transistor and the gate of the second select transistor or the gate of the third select transistor.

公开(公告)号：US09685211B2

公开(公告)日：2017-06-20

申请号：US15018180

申请日：2016-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeunghwan Park ,  Sunghoon Kim

IPC: G11C5/06 ,  G11C7/18 ,  G11C16/26 ,  H01L27/02 ,  G11C5/02 ,  G11C7/10 ,  H01L27/11573 ,  H01L27/11582

CPC classification number: G11C7/18 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1039 ,  G11C7/106 ,  G11C16/26 ,  H01L27/0207 ,  H01L27/11573 ,  H01L27/11582

Abstract: The inventive concepts relate to nonvolatile memory devices. The nonvolatile memory devices may include a memory cell array, and a page buffer circuit connected to the memory cell array through bit lines. The page buffer circuit may comprise a substrate, bit line selection transistors on the substrate and connected to respective ones of the bit lines, and latches on the substrate connected to the bit line selection transistors through lines. The lines may be on a first plane above and parallel to a top surface of the substrate, and may be connected to respective ones of the bit line selection transistors through first contacts. The bit lines may be on a second plane above and parallel to a top surface of the substrate, and may be connected to respective ones of the bit line selection transistors through second contacts.