公开(公告)号：US20220357410A1

公开(公告)日：2022-11-10

申请号：US17732819

申请日：2022-04-29

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation

Inventor： JUNICHI HASEGAWA ,  AKIMASA NIWA

IPC: G01R31/52 ,  H03K17/082

Abstract: A circuit for detecting a leakage current in a semiconductor element includes a setting circuit and a detector. The semiconductor element includes a first terminal at a high-potential-side of the semiconductor element, a second terminal at a low-potential-side of the semiconductor element, and a control terminal. The control terminal receives a signal for controlling a conduction state between the first terminal and the second terminal. The setting circuit sets a duration during which a charging current flows to the control terminal as an undetectable duration, in response to turning on the semiconductor element. The detector outputs a detected signal based on a condition that the leakage current flowing from the control terminal to the second terminal, after the undetectable duration has been elapsed.

公开(公告)号：US20220344906A1

公开(公告)日：2022-10-27

申请号：US17724570

申请日：2022-04-20

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation ,  QD LASER, Inc.

Inventor： Hiroyuki TARUMI ,  Yuki KAMATA ,  Keizo TAKEMASA ,  Kenichi NISHI ,  Yutaka OHNISHI

IPC: H01S5/34 ,  H01S5/343

Abstract: An optical semiconductor device includes an active layer having a plurality of quantum dot layers. The plurality of quantum dot layers includes at least one quantum dot player doped with a p-type impurity. Further, the plurality of quantum dot layers includes at least two quantum dot layers having different emission wavelengths and different p-type impurity concentrations.

公开(公告)号：US20220319998A1

公开(公告)日：2022-10-06

申请号：US17679603

申请日：2022-02-24

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation

Inventor： Shohei Nagai

IPC: H01L23/538 ,  H01L25/07 ,  H01L25/18 ,  H01L23/367 ,  H01L25/16

Abstract: A semiconductor device includes: a substrate main body having a first surface and a second surface; an electric component arranged in the substrate main body; a first terminal and a second terminal arranged on the first surface or the second surface, respectively; a first internal conductor pattern arranged in a first circuit layer arranged between the electric component and the first surface, and electrically connected to the first terminal and the electric component; and a second internal conductor pattern arranged in a second circuit layer arranged between the electric component and the second surface, and electrically connected to the second terminal and the electric component. The first internal conductor pattern and the second internal conductor pattern are at least partially opposed to each other inside the substrate main body.

公开(公告)号：US20220310549A1

公开(公告)日：2022-09-29

申请号：US17688992

申请日：2022-03-08

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation

Inventor： Shohei NAGAI

IPC: H01L23/00

Abstract: A semiconductor device includes a substrate, a semiconductor element and a tin-based solder layer. The semiconductor element faces the substrate in a normal direction of the substrate. The normal direction corresponds to a normal line of the substrate. The tin-based solder layer joins the semiconductor element to the substrate. The tin-based solder layer a central portion and a peripheral portion surrounding the central portion. The tin-based solder layer has a tin crystal with a C-axis at each of the central portion and the peripheral portion. The C-axis at the central portion intersects the normal line at an angle larger than 45 degrees with respect to the normal line. The C-axis at the peripheral portion either intersects the normal line at an angle smaller than or equal to 45 degrees with respect to the normal line, or is parallel to the normal line.

公开(公告)号：US20220304198A1

公开(公告)日：2022-09-22

申请号：US17684469

申请日：2022-03-02

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation

Inventor： Shohei NAGAI

IPC: H05K7/20 ,  H01L23/473 ,  H02M7/537

Abstract: A power converter includes: a semiconductor module that includes a semiconductor element for power conversion, the semiconductor module having a module surface on which an input terminal electrically connected to the semiconductor element is disposed; a capacitor in which a capacitor terminal is disposed, the capacitor having a capacitor surface facing the module surface; a cooler that is disposed between the semiconductor module and the capacitor; and a connecting member that electrically connects the input terminal and the capacitor terminal.

公开(公告)号：US20220285219A1

公开(公告)日：2022-09-08

申请号：US17680464

申请日：2022-02-25

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation ,  HAMAMATSU PHOTONICS K.K.

Inventor： MASATAKE NAGAYA ,  DAISUKE KAWAGUCHI

IPC: H01L21/78 ,  H01L23/544 ,  H01L21/784 ,  H01L21/26

Abstract: A manufacturing method for a semiconductor chip includes: preparing a GaN wafer; producing a processed wafer by forming an epitaxial film on a surface of the GaN wafer to have chip formation regions adjacent to a first surface of the processed wafer; forming a first surface-side element component of a semiconductor element in each chip formation region; forming a wafer transformation layer along a planar direction of the processed wafer by irradiating an inside of the processed wafer with a laser beam; dividing the processed wafer at the wafer transformation layer into a chip formation wafer and a recycle wafer; extracting a semiconductor chip from the chip formation wafer; and after the preparing the GaN wafer and before the dividing the processed wafer, irradiating an inside of the gallium nitride wafer or the processed wafer with a laser beam to form a mark by deposition of gallium.

公开(公告)号：US20220270882A1

公开(公告)日：2022-08-25

申请号：US17590988

申请日：2022-02-02

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation ,  Kochi Prefectural Public University Corporation

Inventor： Hidemoto TOMITA ,  Takashi OKAWA ,  Toshiyuki KAWAHARAMURA ,  Li LIU

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/51

Abstract: A switching includes a gallium nitride semiconductor and a gate insulation film. The gate insulation film is made of silicon oxide and disposed above the gallium nitride semiconductor layer. An interface between the gallium nitride insulation film and the gate insulation film is either free of a gallium oxide layer or provided with the gallium oxide layer with a thickness of 1 nanometer or smaller.

公开(公告)号：US20220246474A1

公开(公告)日：2022-08-04

申请号：US17583754

申请日：2022-01-25

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation

Inventor： Hiroki MIYAKE ,  Tatsuji NAGAOKA

IPC: H01L21/78 ,  H01L21/425 ,  H01L21/479

Abstract: A method for manufacturing a semiconductor device includes: preparing a substrate made of a compound semiconductor containing a first element and a second element that is bonded to the first element and has an electronegativity smaller than that of the first element by 1.5 or more; causing an electric current to flow in the substrate; and dividing the substrate at a position including a current region where the electric current is caused to flow and along a cleavage plane of the substrate. A method for manufacturing a semiconductor device includes: stacking a first substrate and a second substrate each made of the compound semiconductor; and bonding the first substrate and the second substrate by causing an electric current to flow between the first substrate and the second substrate.

公开(公告)号：US20220093748A1

公开(公告)日：2022-03-24

申请号：US17398060

申请日：2021-08-10

Applicant: DENSO CORPORATION ,  MIRISE Technologies Corporation ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Hiroki MIYAKE

IPC: H01L29/36 ,  H01L29/24 ,  H01L21/425

Abstract: A semiconductor device includes: a first semiconductor layer having an N conductive type and made of a gallium oxide-based semiconductor; and a second semiconductor layer made of a gallium oxide-based semiconductor, in contact with the first semiconductor layer, and having the N conductive type with an electrically active donor concentration higher than an electrically active donor concentration of the first semiconductor layer. A difference between a donor concentration of the first semiconductor layer and a donor concentration of the second semiconductor layer is smaller than a difference between the electrically active donor concentration of the first semiconductor layer and the electrically active donor concentration of the second semiconductor layer.

公开(公告)号：US12283619B2

公开(公告)日：2025-04-22

申请号：US17591012

申请日：2022-02-02

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation ,  Kochi Prefectural Public University Corporation

Inventor： Takashi Okawa ,  Hidemoto Tomita ,  Toshiyuki Kawaharamura ,  Li Liu

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28

Abstract: A method for manufacturing a nitride semiconductor device includes formation of a gate insulation film above a nitride semiconductor layer. The formation of the gate insulation film includes formation of silicon oxynitride film in contact with a surface of the nitride semiconductor layer. The formation of the silicon oxynitride film includes oxidation of a film source material having both of silicon and nitride in a molecule to form the silicon oxynitride film.