公开(公告)号：US20120273935A1

公开(公告)日：2012-11-01

申请号：US13097851

申请日：2011-04-29

Applicant: Stefan Martens ,  Tze Yang Hin ,  Kian Pin Queck ,  Kathleen Ong ,  Chin Wei Ronnie Tan ,  Beng Keh See ,  Ulrich Krumbein ,  Horst Theuss

Inventor： Stefan Martens ,  Tze Yang Hin ,  Kian Pin Queck ,  Kathleen Ong ,  Chin Wei Ronnie Tan ,  Beng Keh See ,  Ulrich Krumbein ,  Horst Theuss

IPC: H01L23/498 ,  H01L21/50 ,  H01L21/78

CPC classification number: H01L24/13 ,  H01L21/6836 ,  H01L24/11 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/11002 ,  H01L2224/11009 ,  H01L2224/11622 ,  H01L2224/13007 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13181 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/8182 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/01047 ,  H01L2224/11 ,  H01L2924/00

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are disclosed. An embodiment comprises forming a bump on a die, the bump having a solder top, melting the solder top by pressing the solder top directly on a contact pad of a support substrate, and forming a contact between the die and the support substrate.

Abstract translation: 公开了半导体器件和制造半导体器件的方法。 一个实施例包括在模具上形成凸块，凸块具有焊料顶部，通过将焊料顶部直接压在支撑衬底的接触焊盘上并在模具和支撑衬底之间形成接触来熔化焊料顶部。

公开(公告)号：US07952207B2

公开(公告)日：2011-05-31

申请号：US11950431

申请日：2007-12-05

Applicant: Virendra R. Jadhav ,  Jayshree Shah ,  Kamalesh K. Srivastava

Inventor： Virendra R. Jadhav ,  Jayshree Shah ,  Kamalesh K. Srivastava

IPC: H01L23/52

CPC classification number: H01L23/49816 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09436 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Disclosed are embodiments of a flip-chip assembly and method using lead-free solder. This assembly incorporates mushroom-plated metal layers that fill and overflow solder resist openings on an organic laminate substrate. The lower portion of metal layer provides structural support to its corresponding solder resist opening. The upper portion (i.e., cap) of each metal layer provides a landing spot for a solder joint between an integrated circuit device and the substrate and, thereby, allows for enhanced solder volume control. The additional structural support, in combination with the enhanced solder volume control, minimizes strain on the resulting solder joints. Additionally, the cap further allows the minimum diameter of the solder joint on the substrate-side of the assembly to be larger than the diameter of the solder resist opening. Thus, the invention decouples C4 reliability concerns from laminate design concerns and, thereby, allows for greater design flexibility.

Abstract translation: 公开了使用无铅焊料的倒装芯片组装和方法的实施例。 该组件包括在有机层压基板上填充和溢出阻焊剂开口的蘑菇镀金属层。 金属层的下部为其相应的抗焊剂开口提供结构支撑。 每个金属层的上部（即盖）为集成电路器件和衬底之间的焊接点提供着陆点，从而允许增强的焊料体积控制。 额外的结构支撑与增强的焊料体积控制相结合，最大限度地减少了所得到的焊点的应变。 此外，帽还允许组件的衬底侧上的焊点的最小直径大于阻焊剂开口的直径。 因此，本发明将C4可靠性问题与层压板设计问题分开，从而允许更大的设计灵活性。

公开(公告)号：US20080296761A1

公开(公告)日：2008-12-04

申请号：US12132628

申请日：2008-06-04

Applicant: Jin-Yuan Lee ,  Chien-Kang Chou ,  Shih-Hsiung Lin ,  Hsi-Shan Kuo

Inventor： Jin-Yuan Lee ,  Chien-Kang Chou ,  Shih-Hsiung Lin ,  Hsi-Shan Kuo

IPC: H01L23/485 ,  H01L21/60

CPC classification number: H01L25/0657 ,  H01L24/11 ,  H01L24/13 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05684 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11906 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13123 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/013

Abstract: A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive cylinder and a solder block. The conductive cylinder is formed over the bonding pad of the silicon chip and the solder block is attached to the upper end of the conductive cylinder. The solder block has a melting point lower than the conductive cylinder. The solder block can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive cylinders and finally a solder block is attached to the end of each conductive cylinder.

Abstract translation: 圆柱形粘结结构及其制造方法。 在硅芯片的接合焊盘上形成圆柱形接合结构，并且在形成倒装芯片封装的过程中将芯片翻转以与衬底板连接。 圆柱形接合结构主要包括导电圆柱体和焊料块。 导电圆柱体形成在硅芯片的接合焊盘上，并且焊接块附接到导电圆柱体的上端。 焊料块的熔点低于导电圆柱体。 焊料块可以配置成圆柱形，球形或半球形。 为了制造圆柱形接合结构，在硅晶片上形成具有与位于晶片上的接合焊盘相对应的多个开口的图案化掩模层。 将导电材料沉积到开口中以形成导电圆柱体，最后在每个导电圆柱体的末端附着焊块。

公开(公告)号：US20050062169A1

公开(公告)日：2005-03-24

申请号：US10668986

申请日：2003-09-22

Applicant: Valery Dubin ,  Sridhar Balakrishnan ,  Mark Bohr

Inventor： Valery Dubin ,  Sridhar Balakrishnan ,  Mark Bohr

IPC: H01L21/288 ,  H01L21/60 ,  H01L23/485 ,  H01L23/48

CPC classification number: H01L24/13 ,  H01L21/288 ,  H01L21/4853 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11614 ,  H01L2224/13026 ,  H01L2224/13084 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13564 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/29111 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

Abstract translation: 与模具包装相关的方法，技术和结构。 在一个示例性实施例中，管芯封装互连结构包括半导体衬底和与半导体衬底接触的第一导电层。 第一导电层可以包括基底层金属。 基底层金属可以包括Cu。 示例性实施方式还可以包括与第一导电层接触的扩散阻挡层和在扩散阻挡层顶部的润湿层。 凸起层可以驻留在润湿层的顶部，其中凸起层可以包括Sn，并且Sn可以被电镀。 扩散阻挡层可以是无电解的并且可以适于防止Cu和Sn扩散通过扩散阻挡层。 此外，扩散阻挡层可以进一步适于抑制凸块层中的晶须型形成。

公开(公告)号：US20020185735A1

公开(公告)日：2002-12-12

申请号：US10205118

申请日：2002-07-25

Applicant: International Business Machines Corporation

Inventor： Hiroyuki Sakurai ,  Keizo Sakurai

IPC: H01L021/44 ,  H01L021/443 ,  H01L023/488

CPC classification number: H01L24/11 ,  H01L24/45 ,  H01L2224/1134 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85065 ,  H01L2224/85075 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  Y10T29/53204 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/48 ,  H01L2924/01008 ,  H01L2924/01001 ,  H01L2924/01007 ,  H01L2224/0401

Abstract: A bump connection is formed by stacking at least two metallic balls of different kinds of metals on a conductor of an electronic component such as a semiconductor device. The bump connection is obtained by forming the metallic balls using metallic wires. An apparatus for forming the connection includes a support, capillary member for having a wire pass therethrough, a pair of clamps for clamping the wire, and a nulltorchnull (e.g., electrode, gas flame) which heats the tip of the wire, forming the ball. Successive balls can be formed by this apparatus atop the initially formed ball to provide a stacked configuration.

Abstract translation: 通过在诸如半导体器件的电子部件的导体上堆叠至少两种不同种类的金属的金属球来形成凸点连接。 通过使用金属线形成金属球来获得凸块连接。 一种用于形成连接的装置包括支撑件，用于穿过其中的导线的毛细管构件，用于夹紧线的一对夹具以及加热导线末端的“炬”（例如，电极，气体火焰），形成 球。 该装置可以在初始形成的球体上形成连续的球，以提供堆叠构型。

公开(公告)号：US20020090756A1

公开(公告)日：2002-07-11

申请号：US09969657

申请日：2001-10-04

Inventor： Masamoto Tago ,  Yoshihiro Tomita ,  Kenji Takahashi

IPC: H01L021/48 ,  H01L021/44 ,  H01L023/48

CPC classification number: H01L24/13 ,  H01L23/481 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05609 ,  H01L2224/05616 ,  H01L2224/05647 ,  H01L2224/1134 ,  H01L2224/13009 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/1312 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/1362 ,  H01L2224/13664 ,  H01L2224/45144 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8181 ,  H01L2224/8182 ,  H01L2224/81825 ,  H01L2224/8183 ,  H01L2224/81907 ,  H01L2224/8383 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05611 ,  H01L2224/05144 ,  H01L2224/05155

Abstract: A semiconductor device includes a semiconductor chip. A substrate is arranged in opposition to the semiconductor chip. A first electrode is placed on the semiconductor chip while a second electrode is placed on the substrate. An intermetallic compound layer is arranged between the first electrode and the second electrode. Each of the first and second electrodes is made of predetermined electrode material. The intermetallic compound layer is made of the electrode material and bonding material supplied to at least one of the first and second electrodes.

Abstract translation: 半导体器件包括半导体芯片。 衬底被布置成与半导体芯片相对。 将第一电极放置在半导体芯片上，同时将第二电极放置在基板上。 金属间化合物层布置在第一电极和第二电极之间。 第一和第二电极中的每一个由预定的电极材料制成。 金属间化合物层由提供给第一和第二电极中的至少一个的电极材料和接合材料制成。

公开(公告)号：US20240355691A1

公开(公告)日：2024-10-24

申请号：US18761238

申请日：2024-07-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Cheng Lin ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin

IPC: H01L23/31 ,  B29C45/14 ,  B29K63/00 ,  B29L31/34 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/3114 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/566 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/95 ,  H01L25/0655 ,  B29C45/14655 ,  B29K2063/00 ,  B29K2995/0007 ,  B29L2031/3406 ,  H01L24/13 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13149 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81192 ,  H01L2924/1431 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19101 ,  H01L2924/3511

Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.

公开(公告)号：US20240079313A1

公开(公告)日：2024-03-07

申请号：US18203130

申请日：2023-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyuhyeon CHOI

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49866 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253

Abstract: A semiconductor package includes: a lower substrate including a lower wiring layer; an upper substrate disposed on the lower substrate and including an upper wiring layer and a cavity; an adhesive layer disposed in the cavity; a semiconductor chip having a first surface and a second surface opposite to the first surface, wherein connection pads are disposed on the first surface of the semiconductor chip and are electrically connected to the lower wiring layer, and wherein the second surface of the semiconductor chip is attached to the adhesive layer; a connection structure disposed between the lower substrate and the upper substrate and electrically connecting the lower wiring layer and the upper wiring layer; an encapsulant at least partially surrounding at least a portion of each of the semiconductor chip and the connection structure; and connection bumps electrically connected to the lower wiring layer.

公开(公告)号：US20240014166A1

公开(公告)日：2024-01-11

申请号：US18218886

申请日：2023-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeuk KIM ,  Jaechoon KIM ,  Taehwan KIM ,  Kyungsuk OH ,  Heejung Hwang

IPC: H01L23/00 ,  H01L25/18 ,  H10B80/00 ,  H01L25/00

CPC classification number: H01L24/73 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H10B80/00 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/05155 ,  H01L2224/05073 ,  H01L2224/05564 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/05647 ,  H01L2224/80359 ,  H01L2924/0544 ,  H01L2924/059 ,  H01L2224/06505 ,  H01L2224/08145 ,  H01L2224/13111 ,  H01L2224/13109 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13147 ,  H01L2224/13139 ,  H01L2224/13118 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2924/014 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32013 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/80357 ,  H01L2224/81203 ,  H01L2224/83203 ,  H01L2224/9211 ,  H01L2224/92222 ,  H01L2224/92242 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9222

Abstract: A semiconductor package including: a lower chip; a chip structure including stacked semiconductor chips; and an adhesive film, the semiconductor chips include first bonding chips bonded to each other by bumps and second bonding chips directly bonded to each other, the first bonding chips include: a first bonding lower chip including a first bonding upper pad; and a first bonding upper chip on the first bonding lower chip and including a first bonding lower pad, the second bonding chips include: a second bonding lower chip including a second bonding upper insulating layer and a second bonding upper pad; and a second bonding upper chip on the second bonding lower chip and including a second bonding lower insulating layer, and a second bonding lower pad, and the adhesive film surrounds side surfaces of the bumps, fills a region between the first bonding lower and upper chips, and protrudes from the region.

公开(公告)号：US20230402424A1

公开(公告)日：2023-12-14

申请号：US18207475

申请日：2023-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjin Park

IPC: H01L23/00 ,  H01L25/18 ,  H10B80/00 ,  H01L21/56

CPC classification number: H01L24/73 ,  H01L24/05 ,  H01L25/18 ,  H10B80/00 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L21/56 ,  H01L24/26 ,  H01L24/83 ,  H01L24/92 ,  H01L24/13 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/05669 ,  H01L2224/05644 ,  H01L2224/05554 ,  H01L24/06 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/13155 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13144 ,  H01L2224/13111 ,  H01L2224/13109 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13118 ,  H01L2224/13116 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2224/83201 ,  H01L2224/83365 ,  H01L2224/16059 ,  H01L2224/81201 ,  H01L2224/16227 ,  H01L2924/3841 ,  H01L2224/26122 ,  H01L2224/06131 ,  H01L2224/9211 ,  H01L2224/81815

Abstract: A semiconductor package includes: a base chip including a substrate, an upper protective layer disposed on the substrate, an upper pad disposed on the upper protective layer, and a groove disposed adjacent to the upper pad and in which the upper protective layer is recessed; a semiconductor chip including a connection pad disposed on the upper pad, the semiconductor chip being mounted on the base chip; a bump disposed on the upper pad, and electrically connecting the base chip and the semiconductor chip; and an adhesive film disposed between the base chip and the semiconductor chip, and fixing the semiconductor chip on the base chip, wherein the adhesive film is configured to fill the groove.