公开(公告)号：US20040032359A1

公开(公告)日：2004-02-19

申请号：US10218041

申请日：2002-08-14

Inventor： Semyon Lebedev

IPC: H03M001/38

CPC classification number: H03M1/1023 ,  G11C27/026 ,  H03M1/0682 ,  H03M1/38

Abstract: Briefly, a stage amplifier comprises a differential amplifier having stages and a switch to connect a first differential output of a stage with a second differential output of the stage at a beginning of a conversion cycle.

Abstract translation: 简而言之，舞台放大器包括具有级的差分放大器和在转换周期开始时将级的第一差分输出与级的第二差分输出连接的开关。

公开(公告)号：US06642751B1

公开(公告)日：2003-11-04

申请号：US10236668

申请日：2002-09-06

Applicant: Patrick J. Quinn

Inventor： Patrick J. Quinn

IPC: G11C2702

CPC classification number: G11C27/026

Abstract: A track-and-hold circuit including a pair of circuits each receiving input signals and providing half of a differential output signal. Each of the circuits of the pair includes an amplifier, and a configurable switch circuit coupled to a selectable reference voltages based on an expected input signal type. Each circuit includes a first switched capacitor circuit to sample its respective first input signal in response to a first clock phase, and to couple the sampled first input signal between the output and the negative input of the amplifier in response to a second clock phase. A second switched capacitor circuit samples its respective second input signal relative to an external common mode voltage in response to the first clock phase, and couples the sampled second input signal to a positive amplifier input relative to the selected reference voltage in response to the second clock phase. The amplifiers collectively provide a differential version of the difference between the sampled input signals as shifted by the selected reference voltage.

Abstract translation: 一种跟踪和保持电路，包括一对电路，每对电路接收输入信号并提供差分输出信号的一半。 该对的每个电路包括放大器和基于预期输入信号类型耦合到可选参考电压的可配置开关电路。 每个电路包括第一开关电容器电路，以响应于第一时钟相位对其相应的第一输入信号进行采样，并且响应于第二时钟相位在放大器的输出和负输入之间耦合采样的第一输入信号。 第二开关电容器电路响应于第一时钟相位而相对于外部共模电压对其相应的第二输入信号进行采样，并且响应于第二时钟将采样的第二输入信号相对于所选参考电压耦合到正放大器输入 相。 这些放大器集中地提供被选择的参考电压偏移的采样输入信号之间的差分差分版本。

公开(公告)号：US06587143B1

公开(公告)日：2003-07-01

申请号：US09233018

申请日：1999-01-19

Applicant: David M. Boisvert

Inventor： David M. Boisvert

IPC: H04N5217

CPC classification number: H04N5/361 ,  G11C27/026 ,  H04N5/3575 ,  H04N5/378

Abstract: A correlated double sampler (CDS) circuit having a ping/pong architecture which employs only a single amplifier, and a CCD image sensor output processing circuit including such a CDS circuit and preferably also an analog-to-digital converter for processing the output of the CDS circuit and a black level correction feedback loop. In one cycle of operation (during processing of the raw output of a CCD sensor), the CDS circuit receives a first set of control signals followed by a second set of control signals, its output signal in response to the first set is indicative of the value of one pixel of a sensed image, and its output signal in response to the second set is indicative of the value of the next pixel of the image. Preferably, each set of control signals consists of a clamp signal, a sample signal, and a hold signal. Since the output signal of the CDS circuit has the same offset voltage for all pixels of an image, black level correction can be implemented using only one black level correction feedback loop. Use of a single amplifier (rather than two) and one black level correction loop (rather than two) reduces power consumption. Preferably, the amplifier of the CDS circuit produces a differential output so that the CDS circuit has a better power supply rejection ratio than do conventional CDS circuits. Also preferably, the invention is implemented with CMOS technology as an integrated circuit or portion of an integrated circuit.

Abstract translation: 具有仅使用单个放大器的乒乓架构的相关双采样器（CDS）电路和包括这种CDS电路的CCD图像传感器输出处理电路，并且优选地还包括用于处理 CDS电路和黑电平校正反馈回路。 在一个操作周期（在CCD传感器的原始输出的处理期间），CDS电路接收第一组控制信号，随后是第二组控制信号，其响应于第一组的输出信号指示 感测图像的一个像素的值及其响应于第二组的输出信号表示图像的下一个像素的值。 优选地，每组控制信号由钳位信号，采样信号和保持信号组成。 由于CDS电路的输出信号对于图像的所有像素具有相同的偏移电压，所以可以仅使用一个黑电平校正反馈环来实现黑电平校正。 使用单个放大器（而不是两个）和一个黑电平校正环路（而不是两个）可以降低功耗。 优选地，CDS电路的放大器产生差分输出，使得CDS电路具有比常规CDS电路更好的电源抑制比。 还优选地，本发明通过CMOS技术实现为集成电路或集成电路的一部分。

公开(公告)号：US06570410B2

公开(公告)日：2003-05-27

申请号：US10105681

申请日：2002-03-25

Applicant: Gabriele Manganaro

Inventor： Gabriele Manganaro

IPC: G11C2702

CPC classification number: G11C27/026 ,  H03K5/1515 ,  H03M1/1215

Abstract: The present invention relates to a clock generator circuit which comprises a clock generator subcircuit which is operable to generate two clock signals having approximately the same frequency for use in sampling an analog signal in a generally alternating fashion. The clock generator circuit further comprises a pre-phase clock generator subcircuit associated with the clock generator subcircuit which is operable to generate two pre-phase clock signals, wherein each are associated with a respective one of the two clock signals generated by the clock generator subcircuit. In the pre-phase clock generator circuit, a signal transition of each of the pre-phase clock signals occurs before a signal transition of the respective clock signal generated by the clock generator subcircuit; in addition, a timing of a falling edge of the pre-phase clock signals is dictated by a global clock signal. Thus the clock generator circuit avoids sampling error in a double-sampled sample and hold circuit and harmonic distortion associated therewith.

公开(公告)号：US06549456B2

公开(公告)日：2003-04-15

申请号：US09343117

申请日：1999-06-29

Applicant: Carl W. Werner ,  Andreas M. Haeberli ,  Leon Sea Jiunn Wong ,  Cheng-Yuan Michael Wang ,  Hock C. So ,  Sau C. Wong

Inventor： Carl W. Werner ,  Andreas M. Haeberli ,  Leon Sea Jiunn Wong ,  Cheng-Yuan Michael Wang ,  Hock C. So ,  Sau C. Wong

IPC: G11C1604

CPC classification number: G11C11/5642 ,  G11C5/145 ,  G11C7/16 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/30 ,  G11C16/32 ,  G11C27/005 ,  G11C27/02 ,  G11C27/026

Abstract: Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.

公开(公告)号：US06512399B1

公开(公告)日：2003-01-28

申请号：US09999237

申请日：2001-12-03

Applicant: Gianluigi DeGeronimo ,  Paul O'Connor ,  Anand Kandasamy

Inventor： Gianluigi DeGeronimo ,  Paul O'Connor ,  Anand Kandasamy

IPC: G11C706

CPC classification number: G11C27/026

Abstract: A peak detect-and-hold circuit eliminates errors introduced by conventional amplifiers, such as common-mode rejection and input voltage offset. The circuit includes an amplifier, three switches, a transistor, and a capacitor. During a detect-and-hold phase, a hold voltage at a non-inverting in put terminal of the amplifier tracks an input voltage signal and when a peak is reached, the transistor is switched off, thereby storing a peak voltage in the capacitor. During a readout phase, the circuit functions as a unity gain buffer, in which the voltage stored in the capacitor is provided as an output voltage. The circuit is able to sense signals rail-to-rail and can readily be modified to sense positive, negative, or peak-to-peak voltages. Derandomization may be achieved by using a plurality of peak detect-and-hold circuits electrically connected in parallel.

Abstract translation: 峰值检测和保持电路消除了常规放大器引入的误差，例如共模抑制和输入电压偏移。 该电路包括放大器，三个开关，晶体管和电容器。 在检测和保持阶段期间，放大器的非反相输入端子处的保持电压跟踪输入电压信号，并且当达到峰值时，晶体管被关断，从而在电容器中存储峰值电压。 在读出阶段期间，电路用作单位增益缓冲器，其中存储在电容器中的电压被提供为输出电压。 该电路能够检测轨到轨信号，并且可以容易地修改以检测正，负或峰 - 峰电压。 可以通过使用并联电连接的多个峰值检测和保持电路来实现差分化。

公开(公告)号：US06504406B1

公开(公告)日：2003-01-07

申请号：US09698445

申请日：2000-10-27

Applicant: Hisao Kakitani

Inventor： Hisao Kakitani

IPC: G11C2702

CPC classification number: G11C27/026 ,  G11C27/024

Abstract: In order to reduce harmonic distortion, a track and hold circuit comprising a MOS transistor switch, a hold capacitor, and a voltage stabilizer for biasing bulk potential of the MOS transistor switch at a certain voltage is disclosed.

公开(公告)号：US20020190773A1

公开(公告)日：2002-12-19

申请号：US09880551

申请日：2001-06-13

Inventor： Gabriele Manganaro

IPC: G06F001/04

CPC classification number: G11C27/026 ,  H03K5/1515 ,  H03M1/1215

Abstract: The present invention relates to a clock generator circuit which comprises a clock generator subcircuit which is operable to generate two clock signals having approximately the same frequency for use in sampling an analog signal in a generally alternating fashion. The clock generator circuit further comprises a pre-phase clock generator subcircuit associated with the clock generator subcircuit which is operable to generate two pre-phase clock signals, wherein each are associated with a respective one of the two clock signals generated by the clock generator subcircuit. In the pre-phase clock generator circuit, a signal transition of each of the pre-phase clock signals occurs before a signal transition of the respective clock signal generated by the clock generator subcircuit; in addition, a timing of a falling edge of the pre-phase clock signals is dictated by a global clock signal. Thus the clock generator circuit avoids sampling error in a double-sampled sample and hold circuit and harmonic distortion associated therewith.

公开(公告)号：US20020175844A1

公开(公告)日：2002-11-28

申请号：US09866378

申请日：2001-05-25

Inventor： Elmar Bach ,  Sasan Cyrusian

IPC: H03M001/00

CPC classification number: G11C27/026 ,  G11C27/02 ,  H03M1/1245

Abstract: A sample-and-hold system that includes a first source follower having an input and an output and a second source follower that includes an input connected in series with the output of the first source follower and that furthermore comprises of a sample-and-hold switch connected to an output of the second source follower.

Abstract translation: 一种采样保持系统，其包括具有输入和输出的第一源极跟随器和包括与第一源极跟随器的输出串联连接的输入的第二源极跟随器，并且还包括采样保持器 开关连接到第二源极跟随器的输出端。

公开(公告)号：US20020172069A1

公开(公告)日：2002-11-21

申请号：US10088096

申请日：2002-07-02

Inventor： Michael Thompson ,  Richard Womack

IPC: G11C011/22

CPC classification number: G11C11/22 ,  G11C27/026

Abstract: A sensing device (10) for reading data stored in a passive matrix memory comprising memory cells in the form of ferroelectric capacitors, comprises an integrator circuit (11) for sensing the current response and means (16,17,18) for storing and comparing two consecutive read values, one of which is a reference value. In a read method for use with the sensing device a bit line is connected to the sensing device for sensing a charge flowing therebetween and a memory cell at the crossing of the former and an activated word line, whereafter two consecutive reads of the memory cell are performed an integrated over predetermined time periods in order to generate first and second read values which are compared for determining a logical value dependent on the sensed charge.

Abstract translation: 一种用于读取存储在包括铁电电容器形式的存储单元的无源矩阵存储器中的数据的感测装置（10），包括用于感测电流响应的积分器电路（11）和用于存储和比较的装置（16,17,18） 两个连续的读取值，其中一个是参考值。 在与感测装置一起使用的读取方法中，位线连接到感测装置，用于感测在其间流动的电荷和在前者与激活字线交叉处的存储器单元，之后存储器单元的两个连续读取是 在预定时间周期内执行积分，以便产生第一和第二读取值，所述第一和第二读取值被比较以确定取决于感测到的电荷的逻辑值。