公开(公告)号：US20210013999A1

公开(公告)日：2021-01-14

申请号：US17031822

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Swadesh Choudhary ,  Debendra Das Sharma ,  Mahesh Wagh

IPC: H04L1/00 ,  H04L12/833

Abstract: Systems and devices can include protocol stack circuitry to perform certain methods, including receiving a flow control unit (flit) header and a transaction layer packet (TLP) payload, the TLP payload comprising a first portion and a second portion, determining that the flit header is free from errors, forwarding the flit header and the first portion of the TLP payload to a link partner based on the flit header being free from errors, identifying that the flit contains an error from the second portion of the TLP payload, and sending a data link layer packet (DLLP) to the link partner to indicate the error in the TLP payload.

公开(公告)号：US10860515B2

公开(公告)日：2020-12-08

申请号：US16014012

申请日：2018-06-21

Applicant: Intel Corporation

Inventor： Swadesh Choudhary ,  Bahaa Fahim ,  Mahesh Wagh

IPC: G06F11/00 ,  G06F13/40 ,  G06F11/07 ,  G06F13/42 ,  G06F11/10 ,  G06F11/18

Abstract: Herein is disclosed an integrated input/output (“I/O”) processing system, comprising an I/O port, configured to receive I/O data and to deliver the I/O data to one or more processors; one or more processors, further comprising a first processing logic and a second processing logic, wherein the one or more processors are configured to deliver the received I/O data to the first processing logic and to the second processing logic, and wherein the first processing logic and the second processing logic are configured to redundantly process the I/O data; and a comparator, configured to compare an output of the first processing logic and an output of the second processing logic.

公开(公告)号：US20200319957A1

公开(公告)日：2020-10-08

申请号：US16779391

申请日：2020-01-31

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Robert G. Blankenship ,  Mahesh Wagh ,  Zuoguo Wu

IPC: G06F11/10 ,  H04L29/06 ,  H04L1/00 ,  H04L1/20 ,  G06F13/16

Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

公开(公告)号：US10776302B2

公开(公告)日：2020-09-15

申请号：US16373472

申请日：2019-04-02

Applicant: Intel Corporation

Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

公开(公告)号：US10678736B2

公开(公告)日：2020-06-09

申请号：US15761401

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Zuoguo Wu ,  Mahesh Wagh ,  Mohiuddin M. Mazumder ,  Venkatraman Iyer ,  Jeff C. Morriss

IPC: G06F13/366 ,  G06F13/40 ,  H01L25/065 ,  G06F13/42 ,  H01L23/538

Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

公开(公告)号：US10180927B2

公开(公告)日：2019-01-15

申请号：US15158265

申请日：2016-05-18

Applicant: Intel Corporation

Inventor： Akshay G. Pethe ,  Mahesh Wagh ,  Manjari Kulkarni

IPC: G06F13/40 ,  G06F13/42

Abstract: A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device includes a first protocol stack and a second protocol stack which are each for a PCIe™ communication protocol. The first protocol stack and a second protocol stack may interface, respectively, with a first physical (PHY) layer and a second PHY layer of the device. The first protocol stack and the second protocol stack may exchange packets to facilitate communications via both the first PHY layer and the second PHY layer. In another embodiment, the first PHY layer is for communication according to the PCIe™ communication protocol and the second PHY layer is for communication according to another, comparatively low power communication protocol.

公开(公告)号：US10146291B2

公开(公告)日：2018-12-04

申请号：US14757924

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Robert E. Gough

IPC: G06F1/32 ,  G06F9/44 ,  H04L12/933 ,  G06F13/42 ,  G06F9/4401

Abstract: A serial point-to-point link interface to enable communication between a processor and a device, the high speed serial point-to-point link interface including a transmitter to transmit serial data, a receiver to deserialize serial data, and control logic to implement a protocol stack. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is maintained, and a second off state, in which the supply voltage is not to be provided to the device. The protocol stack provides a default recovery time to allow the device to begin a transition from the first off state to the active state prior to accessing the device. The protocol stack further provides for accessing the device prior to expiration of the default recovery time to complete the transition based on a device-advertised recovery time.

公开(公告)号：US09952644B2

公开(公告)日：2018-04-24

申请号：US14986580

申请日：2015-12-31

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Lily Pao Looi

IPC: G06F1/00 ,  G06F1/32 ,  G06F9/44 ,  G06F13/42

CPC classification number: G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/325 ,  G06F1/3275 ,  G06F1/3278 ,  G06F1/3287 ,  G06F9/4418 ,  G06F13/4265 ,  G06F13/4282 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D10/44

Abstract: Methods and apparatus relating to device power management state transition latency advertisement for faster boot time are described. In some embodiments, a storage unit stores a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state. The first agent writes the value to the storage unit and a second agent waits for the requisite transition delay period (after the first agent initiates its exit from the low power consumption state) before the second agent attempts to communicate with the first agent via a link. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170235701A1

公开(公告)日：2017-08-17

申请号：US15503097

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Akshay Pethe ,  Mahesh Wagh ,  David Harriman ,  Su Wei Lim ,  Debendra Das Sharma ,  Daniel Froelich ,  Venkatraman Iyer ,  James Jaussi ,  Zuoguo Wu

IPC: G06F13/42 ,  G06F13/38

CPC classification number: G06F13/4286 ,  G06F13/385 ,  G06F13/4027 ,  G06F2213/0042 ,  G06F2213/4002

Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques include an apparatus for sideband signaling including a first serial sideband link module and a second serial sideband link module. The first serial sideband link module is to propagate packets from an upstream port to a downstream port via a first signaling lane, and the second serial sideband link module is to propagate packets from the downstream port to the upstream port via a second signaling lane.

公开(公告)号：US09736276B2

公开(公告)日：2017-08-15

申请号：US14310164

申请日：2014-06-20

Applicant: INTEL CORPORATION

Inventor： Mahesh Wagh ,  Abhishek Singhal ,  Jasmin Ajanovic

IPC: H04L29/06 ,  G06F13/38

CPC classification number: H04L69/22 ,  G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: In one embodiment, the present invention includes a fabric on a first semiconductor die to communicate with at least one agent on the die according to an on-chip protocol and a packetization layer coupled to the fabric to receive command and data information from the fabric on multiple links and to packetize the information into a packet for transmission from the die to another die via an in-package packetized link. Other embodiments are described and claimed.