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    Programmable control apparatus
    4.
    发明授权
    Programmable control apparatus 失效
    可编程控制装置

    公开(公告)号：US3886528A

    公开(公告)日：1975-05-27

    申请号：US44563874

    申请日：1974-02-25

    申请人： SPRECHER & SCHUH AG

    发明人： IRANI JAMSHED ,  END EDUARD

    IPC分类号： G05B19/05 ,  G11C13/00

    CPC分类号： G05B19/05 ,  G05B2219/1125 ,  G05B2219/13015 ,  G05B2219/13142 ,  G05B2219/14089 ,  G05B2219/14112 ,  G05B2219/14143 ,  G05B2219/15049

    摘要： Programmable control apparatus provided with a plurality of addressed program lines each having a respective read-out storage for the preserved storage at addressed storage positions or locations of coded command and address information characterizing the individual steps of a flow diagram. A respective stepping or indexing storage delivers the address signals for the storage positions of the read-out storage. The addressed program blocks and the stepping storages are interconnected through a common program address line, a common command line and a common stepping or indexing-control signal line. Further, a central station or device contains a clock generator which generates in successive periods a respective predetermined number of time-displaced clock signals which do not intersect one another, a cyclically throughcounting program address counter with which there is connected the program address line, a command register with which there is connected the command line, a control logic for the evaluation of decoded command signals and connected by a command-decoding circuit with the command register, and at which control logic there are connected the input stages by means of a common inputinformation line and the output stages by means of a common output-information line, and an address storage (anti-clockwise storage) with random access for a command-dependent storage of program block addresses. Further, for each program block there is provided at least one timing circuit, and during each period of clock signals the program address counter is indexed further by one by means of the first clock signal, by means of the second clock signal the command register is read-in, by means of at least one terminal clock signal according to the momentary program block addresses provided for the relevant program block there is controlled at least one timing circuit, and by means of the remaining clock signals there is controlled the period of the control logic as a function of the read-in command signals, so that during each counting cycle of a program address counter all program blocks are sampled and during each period there is carried out a command.