Controlling access to memory cells

    公开(公告)号:US11500553B2

    公开(公告)日:2022-11-15

    申请号:US17160607

    申请日:2021-01-28

    Abstract: A processor can determine that a set of the memory cells is controlled by signals from a first portal. The processor can determine a function of a second portal in a relationship between the first portal and the second portal. The processor can cause, in response to a determination that the function of the second portal is a specific function, a memory control circuitry to be configured so that a subset, of the set, is controlled also by signals from the second portal. The processor can determine a function of a third portal in a relationship between the first portal and the third portal. The processor can cause, in response to a determination that the function of the third portal is the specific function, the memory control circuitry to be configured so that the subset, of the set, is controlled also by signals from the third portal.

    CONTROLLING ACCESS TO MEMORY CELLS
    2.
    发明申请

    公开(公告)号:US20200097193A1

    公开(公告)日:2020-03-26

    申请号:US16139162

    申请日:2018-09-24

    Abstract: A processor can determine that a set of the memory cells is controlled by signals from a first portal. The processor can determine a function of a second portal in a relationship between the first portal and the second portal. The processor can cause, in response to a determination that the function of the second portal is a specific function, a memory control circuitry to be configured so that a subset, of the set, is controlled also by signals from the second portal. The processor can determine a function of a third portal in a relationship between the first portal and the third portal. The processor can cause, in response to a determination that the function of the third portal is the specific function, the memory control circuitry to be configured so that the subset, of the set, is controlled also by signals from the third portal.

    CONTROLLING ACCESS TO MEMORY CELLS

    公开(公告)号:US20210255785A1

    公开(公告)日:2021-08-19

    申请号:US17160607

    申请日:2021-01-28

    Abstract: A processor can determine that a set of the memory cells is controlled by signals from a first portal. The processor can determine a function of a second portal in a relationship between the first portal and the second portal. The processor can cause, in response to a determination that the function of the second portal is a specific function, a memory control circuitry to be configured so that a subset, of the set, is controlled also by signals from the second portal. The processor can determine a function of a third portal in a relationship between the first portal and the third portal. The processor can cause, in response to a determination that the function of the third portal is the specific function, the memory control circuitry to be configured so that the subset, of the set, is controlled also by signals from the third portal.

    Rate limiting in a moderation framework of a database system

    公开(公告)号:US10942903B2

    公开(公告)日:2021-03-09

    申请号:US16424934

    申请日:2019-05-29

    Abstract: Some external users in a public on-line community may post excessive numbers of items, causing annoyance to others and unnecessary loading on database resources. A robust moderation framework enables an individual community moderator or admin to specify a set of rules and actions to mitigate this problem. Scalable, performant rate limiting rules employ windowed counters, separately for each rule, with the counters maintained in cache memory resources outside the main database.

    Controlling access to memory cells

    公开(公告)号:US10908826B2

    公开(公告)日:2021-02-02

    申请号:US16139162

    申请日:2018-09-24

    Abstract: A processor can determine that a set of the memory cells is controlled by signals from a first portal. The processor can determine a function of a second portal in a relationship between the first portal and the second portal. The processor can cause, in response to a determination that the function of the second portal is a specific function, a memory control circuitry to be configured so that a subset, of the set, is controlled also by signals from the second portal. The processor can determine a function of a third portal in a relationship between the first portal and the third portal. The processor can cause, in response to a determination that the function of the third portal is the specific function, the memory control circuitry to be configured so that the subset, of the set, is controlled also by signals from the third portal.

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