公开(公告)号：US09680474B1

公开(公告)日：2017-06-13

申请号：US15073389

申请日：2016-03-17

Applicant: Xilinx, Inc.

Inventor： Anil Kumar Kandala ,  Srinivasa L. Karumajji ,  Santosh Yachareni ,  Sandeep Vundavalli ,  Udaya Kumar Bobbili ,  Golla V S R K Prasad

IPC: H03K19/173 ,  H03K19/177

CPC classification number: H03K19/1737 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17784

Abstract: An interconnect element includes: a selection circuit for receiving input signals and having a selection output; a half-latch circuit having an input coupled to the selection output, wherein the half latch circuit comprises a pull-up device; and a common bias circuit coupled to the pull-up device, wherein the common bias circuit is configured to supply a tunable bias voltage to the pull-up device.

公开(公告)号：US10069487B1

公开(公告)日：2018-09-04

申请号：US15463824

申请日：2017-03-20

Applicant: Xilinx, Inc.

Inventor： Anil Kumar Kandala ,  Santosh Yachareni ,  Sandeep Vundavalli ,  Vijay Kumar Koganti ,  Golla V S R K Prasad ,  Udaya Kumar Bobbili

IPC: H03H11/26 ,  H03K3/3565 ,  H03K19/173 ,  H03K19/177

Abstract: A disclosed delay circuit includes a plurality of Schmitt triggers that are serially coupled. A first Schmitt trigger of the plurality of Schmitt triggers is configured to receive an input signal. An output control circuit is coupled to receive output signals of two or more Schmitt triggers of the plurality of Schmitt triggers, the output control circuit configured to select a signal from one of the one or more Schmitt triggers as an output signal. The output signal is a delayed version of the input signal.