公开(公告)号：US10263815B1

公开(公告)日：2019-04-16

申请号：US15837928

申请日：2017-12-11

Applicant: Xilinx, Inc.

Inventor： Kevin Geary ,  Declan Carey ,  Mohamed Elzeftawi

IPC: H04L25/03 ,  H03G3/30 ,  H03K19/177

Abstract: This disclosure relates generally to continuous time linear equalization. In an example of a continuous time linear equalizer, a variable gain circuit includes transistors having gate nodes respectively as a first and a second input node. A first transimpedance circuit is connected between the first input node and a first output node. A second transimpedance circuit is connected between the second input node and a second output node. A source node of each of the first transistor and the second transistor are commonly connected to one another. In the same or another equalizer, output nodes of a first frequency peaking circuit are connected to input nodes of a second frequency peaking circuit. In such a same or another equalizer, an RC feedback circuit has tap-off nodes and summing nodes respectively connected at the output nodes of the first frequency peaking circuit.