公开(公告)号：US20240354003A1

公开(公告)日：2024-10-24

申请号：US18305871

申请日：2023-04-24

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Asheesh Bhardwaj ,  William Leven ,  Varun Tripathi

IPC分类号： G06F3/06 ,  G06N3/0464

CPC分类号： G06F3/0608 ,  G06F3/0646 ,  G06F3/0673 ,  G06N3/0464

摘要： Disclosed herein are systems and methods for providing on-the-fly padding to feature maps of convolutional neural networks (CNNs). In an implementation, a processor first identifies a padding schema for a feature map based on a type of convolution to be performed on the feature map. Next the processor identifies a feature vector from the feature map currently in an associated memory. Then, the processor determines a padding for the feature vector based on the padding schema. Finally, the processor applies the padding to the feature vector while the feature vector is transferred from the associated memory to registers of the suitable computer.

公开(公告)号：US20240202500A1

公开(公告)日：2024-06-20

申请号：US18067089

申请日：2022-12-16

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Varun Tripathi ,  William Leven ,  Pramod Swami

IPC分类号： G06N3/0464

CPC分类号： G06N3/0464

摘要： Disclosed herein are improved systems and methods for accelerated 2D dilated convolution. A processor determines an offset based on a dilation factor of the 2D dilated convolution. The processor selects rows of data from the 2D input in phases based on the offset and loads an input feature panel without overwriting data that has not yet been consumed by the 2D dilated convolution processor. As the 2D dilated convolution processor performs the convolution iterations, the processor continues to load additional data for the convolution. As the convolution iterations are completed, the processor spaces result of the 2D dilated convolution into a matrix such that results of each phase are spaced based on the offset.