POWER REDUCTION FOR SYSTEMS HAVING MULTIPLE RANKS OF MEMORY

    公开(公告)号:US20230236653A1

    公开(公告)日:2023-07-27

    申请号:US18159022

    申请日:2023-01-24

    Abstract: Provided are electronic devices and methods for power reduction in systems with multiple memory ranks. The electronic device includes a memory system including first and second memory ranks and a memory controller connected to the memory system and configured to control power of the memory system. The memory controller being configured to cause the first memory rank to enter an idle power down (IPD) state during memory access in which a data toggle time without a data bubble is equal to or greater than an IPD minimum gain duration in another bank access for the second memory rank.

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