公开(公告)号：US11093393B2

公开(公告)日：2021-08-17

申请号：US16289650

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hien Le ,  Junhee Yoo ,  Vikas Kumar Sinha ,  Robert Bell ,  Matthew Derrick Garrett

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/0815 ,  G06F12/0882 ,  G06F3/06 ,  G06F13/16

Abstract: A system and a method provide a memory-access technique that effectively parallelizes DRAM operations and coherency operations to reduce memory-access latency. The system may include a memory controller, an interconnect and a processor. The interconnect may be coupled to the memory controller. The processor may be coupled to the memory controller through a first path and a second path in which the first path is through the interconnect and the second path bypasses the interconnect. The processor may be configured to send substantially concurrently a memory access request to the memory controller via the first path and send a page activation request or a hint request to the memory controller via the second path so that the DRAM access operations appear to be masked, or hidden by the coherency operations.