公开(公告)号：US20160172057A1

公开(公告)日：2016-06-16

申请号：US14958149

申请日：2015-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Jun HER ,  Dong-Wook KIM ,  Dong-Hak SHIN

IPC: G11C29/38 ,  G11C29/44

CPC classification number: G11C29/38 ,  G11C11/401 ,  G11C29/40 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/785

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows; and a data control circuit configured to, sequentially read a first unit of data from N memory cell rows of the plurality of memory cell rows, generate merged test results by comparing bits read from the first units of the N memory cell rows, and output the merged test results, during the test mode of the semiconductor memory device. Therefore, test time for testing the semiconductor memory device may be greatly reduced because a test device may determine pass/fail of the data of the unit of repair unit on one read operation.

Abstract translation: 半导体存储器件包括：存储单元阵列，包括多个存储单元行; 以及数据控制电路，被配置为从所述多个存储单元行的N个存储单元行顺序地读取第一单位数据，通过比较从所述N个存储单元行的第一单位读取的比特来生成合并的测试结果，并输出 在半导体存储器件的测试模式期间合并的测试结果。 因此，测试半导体存储器件的测试时间可能会大大降低，因为测试设备可以在一次读取操作中确定修复单元的数据的通过/失败。