公开(公告)号：US20180012775A1

公开(公告)日：2018-01-11

申请号：US15613822

申请日：2017-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Mun BYUN ,  Badro IM ,  Hong-Rae KIM ,  Sin-Hae DO ,  Gyeong-Deok PARK

IPC: H01L21/48 ,  H01L21/764 ,  H01L21/308 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8234 ,  H01L21/67

CPC classification number: H01L21/4885 ,  H01L21/28132 ,  H01L21/28194 ,  H01L21/28556 ,  H01L21/308 ,  H01L21/67138 ,  H01L21/764 ,  H01L21/768 ,  H01L21/823475

Abstract: In a method of manufacturing a semiconductor memory device, a plurality of first conductive structures including a first conductive pattern and a hard mask are sequentially stacked on a substrate. A plurality of preliminary spacer structures including first spacers, sacrificial spacers and second spacers are sequentially stacked on sidewalls of the conductive structures. A plurality of pad structures are formed on the substrate between the preliminary spacer structures, and define openings exposing an upper portion of the sacrificial spacers. A first mask pattern is formed to cover surfaces of the pad structures, and expose the upper portion of the sacrificial spacers. The sacrificial spacers are removed to form first spacer structures having respective air spacers, and the first spacer structures include the first spacers, the air spacers and the second spacers sequentially stacked on the sidewalls of the conductive structures.