公开(公告)号：US20190067228A1

公开(公告)日：2019-02-28

申请号：US16052383

申请日：2018-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Min SON ,  Jeong-Gi JIN ,  Jin-Ho AN ,  Jin-Ho CHUN ,  Kwang-Jin MOON ,  Ho-Jin LEE

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/485

Abstract: A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

公开(公告)号：US20210375725A1

公开(公告)日：2021-12-02

申请号：US17403154

申请日：2021-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-ll CHOI ,  Kwang-Jin MOON ,  Byung-Lyul PARK ,  Jin-Ho AN ,  Atsushi FUJISAKI

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a preliminary via structure through a portion of a substrate; partially removing the substrate to expose a portion of the preliminary via structure; forming a protection layer structure on the substrate to cover the portion of the preliminary via structure that is exposed; partially etching the protection layer structure to form a protection layer pattern structure and to partially expose the preliminary via structure; wet etching the preliminary via structure to form a via structure; and forming a pad structure on the via structure to have a flat top surface.

公开(公告)号：US20210005565A1

公开(公告)日：2021-01-07

申请号：US17029639

申请日：2020-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Min SON ,  Jeong-Gi JIN ,  Jin-Ho AN ,  Jin-Ho CHUN ,  Kwang-Jin MOON ,  Ho-Jin LEE

IPC: H01L23/00 ,  H01L23/485 ,  H01L23/522

Abstract: A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

公开(公告)号：US20190131228A1

公开(公告)日：2019-05-02

申请号：US16106645

申请日：2018-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Ho CHUN ,  Seong-Min SON ,  Hyung-Jun JEON ,  Kwang-Jin MOON ,  Jin-Ho AN ,  Ho-Jin LEE ,  Atsushi FUJISAKI

IPC: H01L23/498 ,  H01L23/525 ,  H01L23/532 ,  H01L23/31 ,  H01L21/768 ,  H01L23/00

Abstract: A semiconductor device and a method of manufacturing the same, the device including a through-hole electrode structure extending through a substrate; a redistribution layer on the through-hole electrode structure; and a conductive pad, the conductive pad including a penetrating portion extending through the redistribution layer; and a protrusion portion on the penetrating portion, the protrusion portion protruding from an upper surface of the redistribution layer, wherein a central region of an upper surface of the protrusion portion is flat and not closer to the substrate than an edge region of the upper surface of the protrusion portion.

公开(公告)号：US20180122721A1

公开(公告)日：2018-05-03

申请号：US15661135

申请日：2017-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SON-KWAN HWANG ,  Ho-Jin LEE ,  Kwang-Jin MOON ,  Byung-Lyul PARK ,  Jin-Ho AN ,  Nae-In LEE

IPC: H01L23/48 ,  H01L23/485 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/485 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311

Abstract: A plug structure of a semiconductor chip includes a substrate, an insulating interlayer disposed on the substrate, wherein the insulating interlayer includes a pad structure disposed therein, a via hole penetrating the substrate and the insulating interlayer, wherein the via hole exposes the pad structure, an insulating pattern formed on an interior surface of the via hole, wherein the insulating pattern includes a burying portion, and the burying portion fills a notch disposed in the substrate at the interior surface of the via hole, and a plug formed on the insulating pattern within the via hole, wherein the plug is electrically connected with the pad structure.