公开(公告)号：US12293081B2

公开(公告)日：2025-05-06

申请号：US18310741

申请日：2023-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raghu Vamsi Krishna Talanki ,  Archita Khare ,  Eldho P. Mathew ,  Jin In So ,  Jong-Geon Lee ,  Venkata Ravi Shankar Jonnalagadda ,  Vishnu Charan Thummala

IPC: G06F3/06

Abstract: The present disclosure relates to field of Dual In-Line Memory Modules that discloses method and system for generating memory maps. The method comprises detecting, by computing system, at least one of DIMM and one or more Dynamic Random Access Memory (DRAM) chips associated with computing system. The one or more accelerators are configured in at least one of DIMM and one or more DRAM chips. Further, the method includes determining accelerator information for each of one or more accelerators via at least one of Serial Presence Detect (SPD) and Multi-Purpose Register (MPR) associated with at least one of DIMM and one or more DRAM chips. Method includes generating unique memory map for each of one or more accelerators based on accelerator information of corresponding one or more accelerators. As a result, performance of computing system may be improved as accelerator capabilities of one or more accelerators are effectively utilized.

公开(公告)号：US12223188B2

公开(公告)日：2025-02-11

申请号：US17748564

申请日：2022-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Raghu Vamsi Krishna Talanki ,  Archita Khare ,  Rahul Tarikere Ravikumar ,  Jinin So ,  Jonggeon Lee

IPC: G06F3/06 ,  G06F12/1027

Abstract: A memory interface for interfacing with a memory device includes a control circuit configured to determine whether a trigger event has occurred for initializing one or more memory locations in the memory device, and initialize the one or more memory locations in the memory device with pre-defined data upon determining the trigger event has occurred.