公开(公告)号：US09984623B2

公开(公告)日：2018-05-29

申请号：US15149757

申请日：2016-05-09

Applicant: Samsung Display Co., Ltd.

Inventor： Tae-Hyeong An ,  Ja-Kyoung Jin

IPC: G09G5/10 ,  G09G3/3233 ,  G09G3/3275

CPC classification number: G09G3/3233 ,  G09G3/3275 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0262 ,  G09G2310/08 ,  G09G2320/0247 ,  G09G2330/021 ,  G09G2340/0435

Abstract: An organic light emitting display device includes a display panel including and a plurality of pixels, a gate driver configured to a normal gate signal and an alternative gate signal to the pixels, a data driver configured to provide a data signal to the pixels, an emission control driver configured to an emission control signal to the pixels, and a controller configured to control the gate driver, the data driver, and the emission control driver. Each of the pixels is driven by the normal gate signal in a first driving mode and is driven by the alternative gate signal in a second driving mode. A threshold voltage of a first transistor is compensated in the first driving mode and the threshold voltage of the first transistor is not compensated in the second driving mode.

公开(公告)号：US09837017B2

公开(公告)日：2017-12-05

申请号：US15175986

申请日：2016-06-07

Applicant: Samsung Display Co., Ltd.

Inventor： Su-Hyeong Park ,  Tae-Hyeong An

IPC: G09G3/36 ,  G09G3/3208

CPC classification number: G09G3/3208 ,  G09G3/3266 ,  G09G2300/0426 ,  G09G2310/0286

Abstract: A stage of a gate driver includes a carry generate block configured to output an (N)-th carry signal based on an input signal and to provide the (N)-th carry signal to an (N+1)-th stage; a first output block configured to output an (N)-th gate initialization signal based on the input signal, an input enable signal, and an input disable signal, wherein the input disable signal is inverted with respect to the input enable signal; and a second output block configured to receive the (N)-th gate initialization signal and to output an (N)-th gate signal according to the output of the (N)-th gate initialization signal; the (N)-th gate signal being delayed one horizontal period from the (N)-th gate initialization signal, wherein the gate signals and the gate initialization signals of the stages are selectively output based on the input enable signal and the input disable signal.