公开(公告)号：US20250056991A1

公开(公告)日：2025-02-13

申请号：US18796111

申请日：2024-08-06

Applicant: Samsung Display Co., LTD.

Inventor： YEONG-GYU KIM ,  SEMYUNG KWON ,  CHANG-YEOL LEE ,  WOONGHEE JEONG ,  YOUNGJIN CHO

IPC: H10K59/131 ,  H10K59/124

Abstract: A display device includes a pixel circuit part including a first oxide semiconductor layer, a first gate driver electrically connected to the pixel circuit part, and including a second oxide semiconductor layer at a same layer as the first oxide semiconductor layer, and a first line part electrically connected to the first gate driver, and defining at least one first dummy contact hole adjacent to the second oxide semiconductor layer.

公开(公告)号：US20240113136A1

公开(公告)日：2024-04-04

申请号：US18364571

申请日：2023-08-03

Applicant: Samsung Display Co., LTD.

Inventor： JONGCHUL YOON ,  SUNGHO KIM ,  WOONGHEE JEONG ,  NUREE UM ,  YU-JIN JEON ,  JAEWON CHO

IPC: H01L27/12

CPC classification number: H01L27/1248 ,  H01L27/124 ,  H01L27/1255

Abstract: A display device includes a first electrode disposed on a substrate and extending in a first direction, a via insulating layer disposed on the first electrode and including an opening exposing at least a portion of the first electrode, and a second electrode disposed on the first electrode and the via insulating layer and overlapping the first electrode in the opening.

公开(公告)号：US20190180688A1

公开(公告)日：2019-06-13

申请号：US16034359

申请日：2018-07-13

Applicant: Samsung Display Co., Ltd.

Inventor： TAEHOON YANG ,  JONGCHAN LEE ,  WOONGHEE JEONG

IPC: G09G3/3258 ,  H01L27/32

Abstract: A pixel, wherein: gates of second and fifth transistors receive a first gate signal; gates of third and fourth transistors respectively receive second and third gate signals; first terminals (FTs) of the second to fifth transistors respectively receive a data voltage, reference voltage, initialization voltage, and first power supply voltage (PSV); a second electrode of a second capacitor receives the first PSV; a second terminal (ST) of a light emitting element (LEE) receives a second PSV; a gate of a first transistor, STs of the second and third transistors, and a first electrode of a first capacitor are connected to a first node; STs of the first and fourth transistors, a FT of the LEE, and second and first electrodes respectively of the first and second capacitors are connected to a second node; and a ST of the fifth transistor is connected to a FT of the first transistor.