Display apparatus having a stepped part

    公开(公告)号:US11075231B2

    公开(公告)日:2021-07-27

    申请号:US16807352

    申请日:2020-03-03

    Abstract: Provided is a display apparatus including a substrate and a semiconductor layer including first and second semiconductor layers. A first gate insulating layer is formed on the semiconductor layer. A first gate wiring overlapping the first semiconductor layer is formed on the first gate insulating layer. A second gate insulating layer is formed on the first gate wiring. A second gate wiring overlapping the second semiconductor layer is formed on the second gate insulating layer. A third gate insulating layer covers the second gate wiring. A driving voltage line intersecting the first and second gate wirings is formed on the third gate insulating layer. A data line intersecting the first and second gate wirings is formed on the third gate insulating layer. A short circuit protection area is formed between the first gate wiring, the second gate wiring, the driving voltage line and the data line.

    ORGANIC LIGHT-EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF
    3.
    发明申请
    ORGANIC LIGHT-EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF 有权
    有机发光二极管显示及其制造方法

    公开(公告)号:US20160284267A1

    公开(公告)日:2016-09-29

    申请号:US14924556

    申请日:2015-10-27

    Abstract: An organic light-emitting diode (OLED) display and a method of manufacturing thereof are disclosed. In one aspect, the display includes a scan line formed over a substrate and configured to provide a scan signal. An initialization voltage line has substantially the same pattern as the scan line and is insulated from the scan line. A data line crosses the scan line and is configured to provide a data voltage. A switching transistor is electrically connected to the scan line and the data line, and a driving transistor is electrically connected to the switching transistor and includes a driving gate electrode. A storage capacitor includes a first storage electrode and a second storage electrode overlapping the first storage electrode, wherein the first storage electrode and the driving gate electrode are integrally formed.

    Abstract translation: 公开了一种有机发光二极管(OLED)显示器及其制造方法。 一方面,显示器包括形成在衬底上并被配置为提供扫描信号的扫描线。 初始化电压线具有与扫描线基本相同的图案,并且与扫描线绝缘。 数据线跨越扫描线并被配置为提供数据电压。 开关晶体管电连接到扫描线和数据线,并且驱动晶体管电连接到开关晶体管并且包括驱动栅电极。 存储电容器包括与第一存储电极重叠的第一存储电极和第二存储电极,其中第一存储电极和驱动栅极电极一体形成。

    Display device
    4.
    发明授权

    公开(公告)号:US11925080B2

    公开(公告)日:2024-03-05

    申请号:US17380221

    申请日:2021-07-20

    CPC classification number: H10K59/131 G09G3/3291 H10K59/121

    Abstract: A display device includes a substrate including a display area and a non-display area, a plurality of pixels disposed in the display area, a common voltage supply wiring overlapping the non-display area and disposed on the substrate, a driving voltage supply wiring overlapping the non-display area and disposed on the substrate, and a data voltage supply wiring overlapping the non-display area and electrically connected to the plurality of pixels, where at least one of the common voltage supply wiring and the driving voltage supply wiring includes a chamfered area, the data voltage supply wiring includes a first data voltage supply wiring, a second data voltage supply wiring, and a third data voltage supply wiring, and the first to third data voltage supply wirings are disposed in different layers.

    Display apparatus having a stepped part

    公开(公告)号:US10128279B2

    公开(公告)日:2018-11-13

    申请号:US15091624

    申请日:2016-04-06

    Abstract: Provided is a display apparatus including a substrate and a semiconductor layer including first and second semiconductor layers. A first gate insulating layer is formed on the semiconductor layer. A first gate wiring overlapping the first semiconductor layer is formed on the first gate insulating layer. A second gate insulating layer is formed on the first gate wiring. A second gate wiring overlapping the second semiconductor layer is formed on the second gate insulating layer. A third gate insulating layer covers the second gate wiring. A driving voltage line intersecting the first and second gate wirings is formed on the third gate insulating layer. A data line intersecting the first and second gate wirings is formed on the third gate insulating layer. A short circuit protection area is formed between the first gate wiring, the second gate wiring, the driving voltage line and the data line.

    Display apparatus having a stepped part

    公开(公告)号:US10580805B2

    公开(公告)日:2020-03-03

    申请号:US16157837

    申请日:2018-10-11

    Abstract: Provided is a display apparatus including a substrate and a semiconductor layer including first and second semiconductor layers. A first gate insulating layer is formed on the semiconductor layer. A first gate wiring overlapping the first semiconductor layer is formed on the first gate insulating layer. A second gate insulating layer is formed on the first gate wiring. A second gate wiring overlapping the second semiconductor layer is formed on the second gate insulating layer. A third gate insulating layer covers the second gate wiring. A driving voltage line intersecting the first and second gate wirings is formed on the third gate insulating layer. A data line intersecting the first and second gate wirings is formed on the third gate insulating layer. A short circuit protection area is formed between the first gate wiring, the second gate wiring, the driving voltage line and the data line.

    DISPLAY APPARATUS HAVING A STEPPED PART
    7.
    发明申请

    公开(公告)号:US20190051676A1

    公开(公告)日:2019-02-14

    申请号:US16157837

    申请日:2018-10-11

    Abstract: Provided is a display apparatus including a substrate and a semiconductor layer including first and second semiconductor layers. A first gate insulating layer is formed on the semiconductor layer. A first gate wiring overlapping the first semiconductor layer is formed on the first gate insulating layer. A second gate insulating layer is formed on the first gate wiring. A second gate wiring overlapping the second semiconductor layer is formed on the second gate insulating layer. A third gate insulating layer covers the second gate wiring. A driving voltage line intersecting the first and second gate wirings is formed on the third gate insulating layer. A data line intersecting the first and second gate wirings is formed on the third gate insulating layer. A short circuit protection area is formed between the first gate wiring, the second gate wiring, the driving voltage line and the data line.

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