公开(公告)号：US11730024B2

公开(公告)日：2023-08-15

申请号：US17031018

申请日：2020-09-24

Applicant: Samsung Display Co., LTD.

Inventor： Sang Hoon Oh ,  Seung Gyu Tae ,  Hyun Woo Kang ,  Dong Hyeok Lee ,  Chang Ho Yi

IPC: H10K59/131 ,  H10K59/35

CPC classification number: H10K59/131 ,  H10K59/35

Abstract: A display device may include a first pixel column disposed on a substrate, a second pixel column adjacent to the first pixel column, a third pixel column adjacent to the second pixel column, and a first wiring, a second wiring, and a third wiring respectively and electrically connected to the first pixel column, the second pixel column, and the third pixel column. Each of the first wiring, the second wiring, and the third wiring may include a first line, a second line electrically connected to the first line, the first line and the second line being disposed on different layers, and a third line electrically connected to the second line, the first line, the second line, and the third line being disposed on different layers.

公开(公告)号：US11211407B2

公开(公告)日：2021-12-28

申请号：US16986933

申请日：2020-08-06

Applicant: Samsung Display Co., LTD.

Inventor： Tetsuhiro Tanaka ,  Yeong-Gyu Kim ,  Ki Seong Seo ,  Seung Hyun Lee ,  Chang Ho Yi

IPC: H01L27/12 ,  G09G3/32 ,  H01L27/32

Abstract: A display device includes a polycrystalline semiconductor including a channel, a first electrode, and a second electrode of a driving transistor, a first gate insulating layer, a gate electrode of a driving transistor, a first electrode of a boost capacitor, a second gate insulating layer, a first interlayer insulating layer, an oxide semiconductor including a channel, a first electrode, and a second electrode of a second transistor, a channel, a first electrode, and a second electrode of a third transistor, and a second electrode of a boost capacitor, a third gate insulating layer disposed on the oxide semiconductor, a gate electrode of the second transistor overlapping the channel of the second transistor, a gate electrode of the third transistor overlapping the channel of the third transistor, and a second interlayer insulating layer disposed on the gate electrode of the second transistor and the gate electrode of the third transistor.