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1.发明申请公开(公告)号：US20200161980A1
公开(公告)日：2020-05-21
申请号：US16748328
申请日：2020-01-21
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro PARISI , Nunzio GRECO , Nunzio SPINA , Egidio RAGONESE , Giuseppe PALMISANO
Abstract: A DC-DC converter includes a transformer having primary and secondary windings, a power oscillator applying an oscillating signal to the primary winding to transmit a power signal to the secondary winding, a rectifier obtaining an output DC voltage by rectifying the power signal at the secondary winding, and comparison circuitry generating an error signal representing a difference between the output DC voltage and a reference voltage value. A transmitter connected to the secondary winding performs an amplitude modulation of the power signal at the secondary winding to transmit an amplitude modulated power signal to the primary winding, the amplitude modulation based upon the error signal and modulating a stream of data to the primary winding. A receiver coupled to the primary winding demodulates the amplitude modulated power signal to recover the error signal and the stream of data. An amplitude of the oscillating signal is controlled by the error signal.
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公开(公告)号：US20190305775A1
公开(公告)日：2019-10-03
申请号：US16371919
申请日：2019-04-01
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro PARISI , Nunzio GRECO , Nunzio SPINA , Egidio RAGONESE , Giuseppe PALMISANO
IPC: H03K17/722 , H03B5/06
Abstract: An oscillator is coupled to a first side of a galvanic barrier for supplying thereto an electric supply signal. The oscillator is configured to be alternatively turned on and off as a function of a PWM drive signal applied thereto. A receiver circuit coupled to the galvanic barrier receives therefrom a PWM power control signal. A signal reconstruction circuit coupled between the receiver circuit block and the oscillator provides to the oscillator a PWM drive signal reconstructed from the PWM power control signal. The signal reconstruction circuit includes a PLL circuit coupled to the receiver circuit block and configured to lock to the PWM control signal from the receiver circuit block. A PLL loop within the PLL circuit is sensitive to the PWM drive signal applied to the oscillator. The PLL loop is configured to be opened as a result of the power supply oscillator being turned off.
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公开(公告)号：US20240151844A1
公开(公告)日：2024-05-09
申请号：US18418298
申请日：2024-01-21
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro PARISI , Andrea CAVARRA , Alessandro FINOCCHIARO , Giuseppe PAPOTTO , Giuseppe PALMISANO
CPC classification number: G01S13/584 , G01S7/4056 , G01S13/931 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B5/1293 , H03L7/099 , H03L7/101 , H03L7/103 , H03L7/193
Abstract: A flash analog-to-digital converter (ADC) receives an input control signal and performs coarse tuning of a frequency of an output signal, produced between first and second nodes having an inductance coupled therebetween. The flash ADC quantizes an operating frequency range for the output signal produced between the first and second nodes as M·Δf, where M is an integer from 0 to N−1, where N is a number of intervals into which a frequency range for the output signal is divided, and where Δf is a resulting frequency step produced by the quantizing. The value of M is generated based upon the input control signal and a word controlling switches of a plurality of switched capacitance circuits associated with the first and second nodes to close ones of those switches associated with the control word to coarsely tune the frequency of the output signal.
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公开(公告)号：US20230194694A1
公开(公告)日：2023-06-22
申请号：US18108993
申请日：2023-02-13
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro PARISI , Andrea CAVARRA , Alessandro FINOCCHIARO , Giuseppe PAPOTTO , Giuseppe PALMISANO
CPC classification number: G01S13/584 , G01S7/4056 , G01S13/931 , H03B5/1212 , H03B5/1228 , H03L7/193 , H03B5/1265 , H03B5/1293 , H03L7/099 , H03L7/101 , H03L7/103 , H03B5/1243
Abstract: Disclosed herein is a tunable resonant circuit including an inductance directly electrically connected in series between first and second nodes, a variable capacitance directly electrically connected between the first and second nodes, and a set of switched capacitances coupled between the first and second nodes. The set of switched capacitances includes a plurality of capacitance units, each capacitance unit comprising a first capacitance for that capacitance unit directly electrically connected between the first node and a switch and a second capacitance for the capacitance unit directly electrically connected between the switch and the second node. Control circuitry is configured to receive an input control signal and connected to control the switches of the set of switched capacitances. A biasing circuit is directly electrically connected to the tunable resonance circuit at the first and second nodes.
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Patent Agency Ranking
公开(公告)号：US20200266781A1
公开(公告)日：2020-08-20
申请号：US16793144
申请日：2020-02-18
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro FINOCCHIARO , Giuseppe PAPOTTO , Egidio RAGONESE , Giuseppe PALMISANO
Abstract: A cascade of amplifier stages has a differential input and a differential output. The cascade of amplifier stages includes at least one differential amplifier circuit including first and second transistors, at least one of the first and second transistors having a control terminal and a body terminal. A mismatch between the first and second transistors generates an input offset. A feedback network couples the differential output to the body terminal in order to cancel the input offset. The feedback network includes a low-pass filter and a differential amplifier stage.
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公开(公告)号：US20220329207A1
公开(公告)日：2022-10-13
申请号：US17704919
申请日：2022-03-25
Applicant: STMicroelectronics S.r.l.
Inventor： Nunzio SPINA , Egidio RAGONESE , Giuseppe PALMISANO
Abstract: A rectifier stage includes a differential input transistor pair coupled between a reference voltage node and an intermediate node, and a load circuit coupled between the intermediate node and a supply voltage node. The differential input transistor pair receives a radio-frequency amplitude modulated signal. A rectified signal indicative of an envelope of the radio-frequency amplitude modulated signal is produced at the intermediate node. An amplifier stage coupled to the intermediate node produces an amplified rectified signal at an output node that is indicative of the envelope of the radio-frequency amplitude modulated signal. The rectifier stage includes a resistive element coupled between the intermediate node and the supply voltage node in parallel to the load circuit.
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7.发明申请公开(公告)号：US20200278420A1
公开(公告)日：2020-09-03
申请号：US16795977
申请日：2020-02-20
Applicant: STMicroelectronics S.r.l.
Inventor： Giuseppe PAPOTTO , Egidio RAGONESE , Claudio NOCERA , Alessandro FINOCCHIARO , Giuseppe PALMISANO
Abstract: An input receives a radio frequency (RF) signal having an interfering component superimposed thereon. The RF signal is mixed with a local oscillator (LO) signal and down-converted to an intermediate frequency (IF) to generate a mixed signal which includes a frequency down-converted interfering component. The mixed signal is amplified by an amplifier to generate an output signal. A feedback loop processes the output signal to generate a correction signal for cancelling the frequency down-converted interfering component at the input of the amplifier. The feedback loop includes a low-pass filter and a amplification circuit which outputs the correction signal.
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8.发明公开公开(公告)号：US20240210550A1
公开(公告)日：2024-06-27
申请号：US18594456
申请日：2024-03-04
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro FINOCCHIARO , Alessandro PARISI , Andrea CAVARRA , Giuseppe PAPOTTO , Giuseppe PALMISANO
IPC: G01S13/34 , G01S13/931 , H03B5/12 , H03L7/193
CPC classification number: G01S13/34 , G01S13/931 , H03B5/1231 , H03L7/193
Abstract: A circuit includes a phase-frequency-detector generating first and second digital control signals indicative of phase differences between an input reference-signal and an output-signal, a charge-pump generating a control-signal based upon the first and second digital control signals, and an oscillator-circuit. The oscillator-circuit includes an active core coupled between first and second nodes, with a tunable resonant circuit a set of capacitances selectively connected between the first and second nodes, wherein a tap between the first and second variable capacitances receives the control-signal for tuning the tunable resonant circuit. A timer-circuit generates a timing-signal based upon the input reference-signal and a reset-signal. A calibration-circuit controls which capacitances of the set of capacitances are connected between the first and second nodes, in response to the timing-signal and a comparison between a threshold and a voltage-signal that is based upon auxiliary pulsed currents generated based upon the first and second digital control signals.
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公开(公告)号：US20210376735A1
公开(公告)日：2021-12-02
申请号：US17404382
申请日：2021-08-17
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro PARISI , Nunzio GRECO , Nunzio SPINA , Egidio RAGONESE , Giuseppe PALMISANO
Abstract: A DC-DC converter includes: an transformer having a primary winding and a secondary winding magnetically coupled to the primary winding; a power oscillator applying an oscillating signal to the primary to transmit a power signal to the secondary winding; a rectifier connected to the secondary winding of the transformer to obtain an output DC voltage by rectification of the power signal; comparison circuitry to generate an error signal representing a difference between the output DC voltage and a reference voltage; a transmitter connected to the secondary winding of the transformer to apply an amplitude modulation to the power signal at the secondary winding of the transformer in response to the error signal to thereby produce an amplitude modulated signal at the primary winding; and a receiver and control circuit connected to the primary winding to control an amplitude of the oscillating signal as a function of the amplitude modulated signal.
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