公开(公告)号：US20040061524A1

公开(公告)日：2004-04-01

申请号：US10611322

申请日：2003-07-01

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Manoj Kumar ,  Sunil Chandra Kasanyal

IPC: H03K019/0175

CPC classification number: H03K19/018521

Abstract: A voltage level translator for digital logic circuits provides high level to low level voltage translation with equal rise and fall delays. The voltage level translator may include an input high voltage logic inverter (operating at the high voltage level) and connected to an output low voltage logic inverter operating at the low voltage level via a voltage reduction circuit. A related method for providing high level to low voltage translation may include providing an input inverter operating at the high voltage level and an output inverter operating at the low voltage level. Furthermore, the output of the high voltage inverter may be coupled to the input of the low voltage inverter after reducing the output voltage of the high voltage inverter to the required level.

Abstract translation: 用于数字逻辑电路的电压电平转换器具有相同的上升和下降延迟的高电平到低电平电压转换。 电压电平转换器可以包括输入高压逻辑逆变器（以高电压电平工作），并通过电压降低电路连接到在低电压电平下工作的输出低压逻辑逆变器。 用于提供高电平到低电压平移的相关方法可以包括提供在高电压电平下工作的输入逆变器和在低电压电平下工作的输出逆变器。 此外，在将高压逆变器的输出电压降低到所需水平之后，高压逆变器的输出可以耦合到低压逆变器的输入。