公开(公告)号：US20240130108A1

公开(公告)日：2024-04-18

申请号：US18369552

申请日：2023-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Euichul JEONG ,  Sang-Woon LEE ,  Sangho LEE ,  Moonyoung JEONG

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/05

Abstract: A semiconductor memory device includes a substrate, a bit line on the substrate, word lines provided on the bit line and spaced apart in a first direction parallel to a top surface of the substrate, a back gate electrode provide between a pair of adjacent word lines among the word lines, active patterns provided between the back gate electrode and the pair of adjacent word lines, contact patterns respectively provided on the active patterns, a first back gate insulating pattern provided between the bit line and the back gate electrode, and a second back gate insulating pattern and a third back gate insulating pattern which are provided on the back gate electrode, where the back gate upper insulating pattern includes a material having a first dielectric constant and the back gate lower insulating pattern includes a material having a second dielectric constant that is greater than the first dielectric constant.