公开(公告)号：US20250157902A1

公开(公告)日：2025-05-15

申请号：US18938811

申请日：2024-11-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon KANG ,  Kiju LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538

Abstract: A semiconductor package includes: a first redistribution structure; a second redistribution structure arranged on the first redistribution structure; a first conductive pillar arranged spaced apart from the second redistribution structure and arranged on the first redistribution structure; a first chip arranged on the second redistribution structure; a first molding member covering the first chip and disposed on the second redistribution structure; a third redistribution structure arranged on the first molding member; a second chip arranged on the third redistribution structure; a second molding member covering the first conductive pillar and the first molding member; and a fourth redistribution structure arranged on the second molding member, wherein a first film is arranged on a first surface of the first conductive pillar, and the first film includes tin (Sn).

公开(公告)号：US20220130786A1

公开(公告)日：2022-04-28

申请号：US17342902

申请日：2021-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyoyoung JUNG ,  Jinsu KIM ,  Hyunsuk YANG ,  Kiju LEE ,  Hoyeon JO ,  Ikkyu JIN

IPC: H01L23/00

Abstract: A semiconductor package including a core substrate, a semiconductor chip in the core substrate and having chip pads, a redistribution wiring layer covering a lower surface of the core substrate and including redistribution wirings electrically connected to the chip pads and a pair of capacitor pads exposed from an outer surface of the redistribution wiring layer, conductive pastes on the capacitor pads, respectively, and a capacitor via the conductive pastes and having first and second outer electrodes on the capacitor pads, respectively, may be provided. Each of the capacitor pads includes a pad pattern exposed from the outer surface of the redistribution wiring layer, and at least one via pattern at a lower portion of the pad pattern and electrically connected to at least one of the redistribution wirings. The via pattern is eccentric by a distance from a center line of the pad pattern.

公开(公告)号：US20250167128A1

公开(公告)日：2025-05-22

申请号：US18808327

申请日：2024-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon KANG ,  Kiju LEE

IPC: H01L23/544 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes a package body, a semiconductor chip disposed in the package body, a first redistribution structure disposed on a lower surface of the package body and on a lower surface of the semiconductor chip, wherein the first redistribution structure includes a first redistribution element, a first redistribution pad disposed on a lower surface of the first redistribution structure and electrically connected to the first redistribution element, a ball land layer disposed on a lower surface of the first redistribution pad, a first pad insulating layer disposed on the lower surface of the first redistribution structure, wherein the first pad insulating layer insulates the first redistribution pad and the ball land layer, an alignment mark structure spaced apart from the first redistribution pad and the ball land layer and disposed inside or on a lower surface of the first pad insulating layer, and a first solder ball disposed on a lower surface of each of the first redistribution pad and the ball land layer.

公开(公告)号：US20250149515A1

公开(公告)日：2025-05-08

申请号：US18673864

申请日：2024-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiju LEE ,  Jinwoo PARK

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498

Abstract: A semiconductor package, comprising: a semiconductor chip; a conductive bonding layer on the semiconductor chip; an upper insulating layer on the conductive bonding layer; an upper package on the upper insulating layer; a heat dissipation structure that includes upper heat dissipation patterns and upper heat dissipation vias, wherein the upper heat dissipation patterns are in the upper insulating layer, and the upper heat dissipation vias connect the conductive bonding layer and the upper heat dissipation patterns; and a heat dissipation member on at least one side of the upper package, wherein the heat dissipation member is connected to the upper heat dissipation patterns.