公开(公告)号：US20140002157A1

公开(公告)日：2014-01-02

申请号：US13835824

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Ryun CHOI ,  Ji-Hun OH ,  Choong-Bin LIM

IPC: H03K3/017

CPC classification number: H03K3/017 ,  H03K5/1565

Abstract: A duty cycle error accumulation circuit includes first to nth delay units and a feedback unit. The first to nth delay units receive a clock signal, a first input signal and a second input signal, respectively, to generate a first output signal and a second output signal by delaying one signal selected from first and second input signals based on a logic level of the clock signal. The feedback unit supplies second input signal to a kth delay unit based on second output signal of a (k+1)th delay unit. The first output signal of the kth delay unit is supplied to the (k+1)th delay unit as first input signal, and the clock signal is supplied to the first delay unit as first input signal and to the nth delay unit as second input signal. The duty cycle error accumulation circuit effectively corrects a duty cycle of a clock signal.

Abstract translation: 占空比误差累积电路包括第一至第n延迟单元和反馈单元。 第一至第n延迟单元分别接收时钟信号，第一输入信号和第二输入信号，以通过基于逻辑电平延迟从第一和第二输入信号选择的一个信号来产生第一输出信号和第二输出信号 的时钟信号。 反馈单元基于第（k + 1）个延迟单元的第二输出信号向第k个延迟单元提供第二输入信号。 第k延迟单元的第一输出信号作为第一输入信号提供给第（k + 1）个延迟单元，并且时钟信号作为第一输入信号提供给第一延迟单元，并作为第二输入提供给第n延迟单元 信号。 占空比误差累积电路有效地校正时钟信号的占空比。