公开(公告)号：US11832442B2

公开(公告)日：2023-11-28

申请号：US17493671

申请日：2021-10-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeon Woo Jang ,  Soo Ho Shin ,  Dong Sik Park ,  Jong Min Lee ,  Ji Hoon Chang

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/30

Abstract: The present disclosure provides a semiconductor memory device with improved element performance and reliability. The semiconductor memory device comprises a substrate, a gate electrode extending in a first direction in the substrate, a plurality of buried contacts on the substrate, and a fence in a trench between adjacent ones of the buried contacts. The fence is on the gate electrode. The fence includes a spacer film on side walls of the trench and extending in a second direction intersecting the first direction, and a filling film in the trench and on the spacer film. An upper surface of the spacer film is lower than an upper surface of the filling film with respect to the substrate.