POWER MANAGEMENT CHIP, ELECTRONIC DEVICE HAVING THE SAME, AND OPERATING METHOD THEREOF

    公开(公告)号:US20240072664A1

    公开(公告)日:2024-02-29

    申请号:US18188157

    申请日:2023-03-22

    CPC classification number: H02M3/158 H02M1/0032 H02M1/36 H02M1/0045

    Abstract: A power management chip includes a gate driver configured to output a first gate signal driving a first power switch and a second gate signal driving the second power switch, a multiplexer configured to receive an error detect signal from a first error amplifier and a first gate signal from the gate driver, and drive the first power switch with either of the error detect signal or the first gate signal in response to a mode select signal; an inductor detection logic configured to receive the inductor detect signal, output a comparison detect signal and a pulse signal for detecting an external inductor, and output the mode select signal corresponding to a result of the detecting, and a comparator comparing an internal output voltage of an output node and an output voltage of the feedback node in response to the comparison detect signal.

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