公开(公告)号：US20210183822A1

公开(公告)日：2021-06-17

申请号：US17190113

申请日：2021-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hak-Seung LEE ,  Kwang-Jin Moon ,  Tae-Seong Kim ,  Dae-Suk Lee ,  Dong-Chan Lim

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a substrate having a first via hole, an insulation interlayer formed on the substrate and having a first bonding pad in an outer surface thereof and a second via hole connected to the first via hole and exposing the first bonding pad, and a plug structure formed within the first and second via holes to be connected to the first bonding pad. The second semiconductor chip includes a second bonding pad bonded to the plug structure which is exposed from a surface of the substrate of the first semiconductor chip.

公开(公告)号：US20200161277A1

公开(公告)日：2020-05-21

申请号：US16430625

申请日：2019-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hak-Seung LEE ,  Kwang-Jin Moon ,  Tae-Seong Kim ,  Dae-Suk Lee ,  Dong-Chan Lim

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a substrate having a first via hole, an insulation interlayer formed on the substrate and having a first bonding pad in an outer surface thereof and a second via hole connected to the first via hole and exposing the first bonding pad, and a plug structure formed within the first and second via holes to be connected to the first bonding pad. The second semiconductor chip includes a second bonding pad bonded to the plug structure which is exposed from a surface of the substrate of the first semiconductor chip.