公开(公告)号：US10698083B2

公开(公告)日：2020-06-30

申请号：US15686630

申请日：2017-08-25

Applicant: Raytheon Company

Inventor： Daniel Thompson ,  Harry B. Marr ,  Ian Robinson ,  Jeffrey Caldwell

IPC: G01S7/03 ,  H01Q3/26 ,  G01S7/40 ,  G01S13/02

Abstract: A system and method of digital beamforming for a monobit phased array radar system includes providing a plurality of monobit analog signals received by at least one antenna to at least one field programmable gate array (FPGA). A plurality of monobit SerDes transceivers within the FPGA convert the plurality of monobit analog signals into a plurality of multibit digital signals, each of the multibit digital signals being modified according to a digital signal conditioning value to calibrate, phase align, and synchronize the digital signals. A digital beam is formed by coherently combining the plurality of digital signals within the FPGA.

公开(公告)号：US20190067814A1

公开(公告)日：2019-02-28

申请号：US15686630

申请日：2017-08-25

Applicant: Raytheon Company

Inventor： Daniel Thompson ,  Harry B. Marr ,  Ian Robinson ,  Jeffrey Caldwell

IPC: H01Q3/38 ,  H01Q21/22 ,  G01S13/02

Abstract: A system and method of digital beamforming for a monobit phased array radar system includes providing a plurality of monobit analog signals received by at least one antenna to at least one field programmable gate array (FPGA). A plurality of monobit SerDes transceivers within the FPGA convert the plurality of monobit analog signals into a plurality of multibit digital signals, each of the multibit digital signals being modified according to a digital signal conditioning value to calibrate, phase align, and synchronize the digital signals. A digital beam is formed by coherently combining the plurality of digital signals within the FPGA.