公开(公告)号：US20220115270A1

公开(公告)日：2022-04-14

申请号：US17480746

申请日：2021-09-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya YOSHIDA ,  Tomohiro TOMIZAWA

IPC: H01L21/768 ,  H01L29/66 ,  H01L27/12 ,  H01L21/66

Abstract: A first MISFET is formed on a semiconductor layer of an SOI substrate in a circuit region and a second MISFET composing a TEG for VC inspection is formed on the semiconductor layer of the SOI substrate in a TEG region. An interlayer insulating film is formed, contact holes are formed in the interlayer insulating film, and plugs are formed in the contact holes, respectively. In the TEG region, the plugs include a plug electrically connected to both the semiconductor substrate composing the SOI substrate and the semiconductor layer composing the SOI substrate.