公开(公告)号：US20190205491A1

公开(公告)日：2019-07-04

申请号：US16232583

申请日：2018-12-26

Applicant: RAYTHEON COMPANY

Inventor： Michael Castle ,  Paul Yue ,  PC Chien ,  Lauren Hack ,  Gabriel Andrew Chow

IPC: G06F17/50

CPC classification number: G06F17/5027 ,  G06F17/504

Abstract: A method for modeling a field-programmable gate array (FPGA) for an emulator includes performing a validation process on an FPGA design to determine whether an FPGA emulator is able to emulate at least one component in the FPGA design; responsive to the FPGA emulator being unable to emulate the at least one component in the FPGA design, modifying the FPGA design by replacing the at least one component with at least one replacement component; executing a first simulation of the FPGA design to generate a first output; executing a second simulation of the modified FPGA design to generate a second output; and determining, with reference to the first output and the second output, that the FPGA design and the modified FPGA design are functionally equivalent.