DYNAMIC AFFINITY ROUTING OF INTERRUPTS IN A MULTIPROCESSOR SYSTEM ON A CHIP (SOC)

    公开(公告)号:US20250117346A1

    公开(公告)日:2025-04-10

    申请号:US18482793

    申请日:2023-10-06

    Abstract: Aspects of the disclosure are directed to interrupt handling. In accordance with one aspect, disclosed includes a first processing engine; a second processing engine; and a timeout monitoring block coupled to the first processing engine and the second processing engine, wherein the timeout monitoring block is configured to reaffinitize an interrupt affined to the first processing engine to the second processing engine. Also disclosed for interrupt handling includes placing a first interrupt into a pending state; initiating a handling of a second interrupt; initiating a programmed timeout value; triggering a timeout state of the first interrupt when an interrupt timer reaches the programmed timeout value; and entering a reaffinitization state of the first interrupt after the timeout state is triggered.

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